secriscv'21: 2021 International Workshop on Secure RISC-V Architecture Design Exploration 2021 IEEE International Symposium on Workload Characterization (IISWC) Virtual, AZ, United States, November 7, 2021 |
Conference website | https://secriscv.org/ |
Submission link | https://easychair.org/conferences/?conf=secriscv21 |
Abstract registration deadline | October 16, 2021 |
Submission deadline | October 16, 2021 |
Following the very successful and well-attended SECRISC-V’20, the Secure RISC-V (SECRISC-V) architecture design exploration workshop seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).
Part of the 2021 IEEE International Symposium on Workload Characterization (IISWC), November 7 - November 9, 2021.
Submission Guidelines
Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:
- Secure cores and multicores
- ISA extensions for Security
- Software and hardware obfuscation Techniques
- Hardware security solutions for machine learning
- Secure design for emerging applications: IoT, robotics, wearable computing, etc.
- Architectural designs and hardware security solutions for HPC, Data Centers and cloud computing
- Hardware virtualization and isolation for security
- Hardware-Software co-design solutions: graph analytics,
- Post-quantum cryptosystem designs
- Neuromorphic Architectures
- Blockchain enabled secure computing
- Classic and Modern encryption algorithms and hardware support
- Hardware security support for integrity and authentication, key distribution and management, and trust platform modules
- Secure execution environment
- Memory subsystem organization to secure data accesses
- Network-on-Chip (NoC) security feature to process and compute isolation
The paper must be submitted in PDF format. The content of the submission is limited to four (4) pages - 8.5"x11" single-spaced double-column.
Deadlines
- Submission: October 16, 2021
- Notification: October 23, 2021
- Final Version: November 3, 2021
- Presentation: November 7, 2021
Committees
Organizing Chair
- Michel A. Kinsy and the Secure, Trusted, and Assured Microelectronics (STAM) Center Team at Arizona State University
Program committee
-
Coming soon.
Contact
All questions about submissions should be emailed to secriscv@gmail.com