CFP

ParaFPGA2017: Parallel Computing with FPGAs

Savoia Regency Conference Center

Bologna, Italy, September 12-15, 2017

Conference website	http://parafpga.elis.ugent.be
Submission deadline	June 10, 2017

Topics: high level synthesis reconfigurable computing parallel computing high performance computing

ParaFPGA2017 is a mini-symposium organized in conjunction with the biennial Parallel Computing conference ParCo2017, to be held in Italy on 12-15 September 2017.

Parallel computing with Field Programmable Gate Arrays (ParaFPGA) brings together research on tools, programming environments and using FPGAs for high computing.

High computing requires new avenues and creative solutions to alleviate the power and frequency limitations of today's processors. Accelerators are becoming the mainstream approach for delegating compute intensive tasks to appropriate hardware. The diversity of architectures and high-level synthesis designs are harnessed with common languages such as OpenCL combined with dedicated programming and synthesis environments.

ParaFPGA continues the series of biennial mini-symposia in conjunction with the conference Parallel Computing.

Submission Guidelines

Authors are to submit a full paper (maximum 10 pages) or an extended abstract of minimal 4 pages using the modalities specified at the symposium website http://parafpga.elis.ugent.be. The approved contributions will be presented at the conference and the accepted full papers are published in the ParCo 2017 proceedings.

List of Topics

Original contributions on the use of parallel computing with FPGAs are in areas including but not limited to:

analysis of high-level synthesis
design space exploration using HLS
of parallel techniques with FPGAs e.g. in big data, deep learning, biology and finance
high-level synthesis debugging
domain specific synthesis languages
optimizing memory locality and data paths
partial reconfiguration and optimal ip-core (re)use
managing a run-time library of ip-cores
use of hybrid CPU// systems e.g. in real-time video or automotive systems
modeling and simulation of architectures and

Committees

Program Committee

Ivan Beretta, University of Westminster, UK
Erik D'Hollander, Ghent University, Belgium, (chair)
Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Mike Hutton, Altera, USA
Tsutomu Maruyama, University of Tsukuba, Japan
Christian Pilato, Columbia University, USA
Dionisios Pnevmatikatos, Technical University of Crete, Greece
Viktor Prasanna, University of Southern California, USA
Kyle Rupnow , Advanced Digital Sciences Center, Singapore
Abdellah Touhafi, Vrije Universiteit Brussel, Belgium, (co-chair)
Sotirios G. Ziavras, New Jersey Institute of Technology, USA

Organizing committee

Gerhard R. Joubert (conference chair)
Marco Danelutto (ParCo PC chair)
Patrizio Dazzi (ParCo PC co-chair)
Sanzio Bassini (organising committee chair)
Frans Peters (finance chair)

Publication

All refereed and accepted papers presented at the conference will be published in the proceedings of the ParCo2017 conference subject to the ParCo proceeding guidelines. The proceedings will be published after the conference by IOS Press in the series Advances in Parallel Computing, ISSN 0927-5452.

Papers are written conform the typing instructions and Word or LaTeX templates available on the authors guidelines page.

Venue

The conference will be held in the conference center of the Savoia Hotel Regency,

Contact

All questions about submissions should be emailed to parafpga@elis.ugent.be