![]() | OpenSoC4HE 2027: 1st Workshop on Open System on Chips for Higher Education in Computer Architecture HiPEAC 2027 Glasgow, UK, January 18-19, 2027 |
| Conference web page | https://edge-group-polito.github.io/OpenSoC4HE/ |
| Submission link | https://easychair.org/conferences/?conf=opensoc4he2027 |
| Submission deadline | November 16, 2026 |
Europe's path to digital sovereignty, anchored by the EU Chips Act and the European Processor Initiative (EPI), critically depends on training a new generation of engineers capable of designing and verifying custom silicon. Despite this mandate, computer architecture and digital design courses across European universities still largely rely on closed, vendor-locked toolchains and abstract software simulators. This paradigm leaves graduates one step removed from real-world, modern silicon design flows.
The advent of the open-source hardware movement, particularly the RISC-V instruction set architecture, has catalyzed a shift. Open-source educational Systems-on-Chip (SoCs) are starting to close the pedagogical gap between high-level architectural theory and physical hardware implementation. However, a critical element is still missing: a dedicated venue where the faculty who deploy these platforms in undergraduate and graduate classrooms can meet, compare deployment experiences, exchange teaching materials, and align on a common academic roadmap. OpenSoC4HE fills this gap within the HiPEAC community, placing an explicit focus on the education layer upon which the entire open-silicon stack ultimately depends.
The workshop combines invited talks, contributed papers, a hands-on tutorial on an open educational SoC, poster fast-pitches, and a closing community panel. A shared community roadmap document, drafted live during the panel and published with open access, is the workshop's main deliverable.
List of TopicsList of Topics
Topics of interest include, but are not limited to:
- Open-source educational SoCs and cores
- Course design and curricula built on open hardware (BSc, MSc, PhD)
- Hands-on labs, FPGA prototyping, and bring-your-own-device teaching setups
- Teaching hardware verification (cocotb, UVM, formal methods) alongside RTL design
- RTL-to-GDSII and tape-out experiences in the classroom (open PDKs, MPW shuttles)
- Reusable teaching material, assessment rubrics, and open educational resources
- Bridging digital logic, computer architecture, and SoC integration
- Industry–academia alignment and the semiconductor skills pipeline
- Experience reports: what worked, what failed, and lessons learned
Important DatesImportant Dates
- Submission deadline: November 16, 2026
- Notification of acceptance: December 14, 2026
- Camera-ready version: January 7, 2027
Organizing CommitteeOrganizing Committee
- Salvatore Bramante, IMT School for Advanced Studies Lucca
- Alessandra Dolmeta, Politecnico di Torino
- Luigi Giuffrida, Politecnico di Torino
- Jose Miranda, Universidad Politécnica de Madrid
- Tobias Scheipel, Graz University of Technology
- Alessandro Cilardo, Università di Napoli Federico II
- José Flich, Universitat Politècnica de València
Submission Guidelines
All contributions must be submitted in PDF through EasyChair: https://easychair.org/conferences/?conf=opensoc4he2027
Authors select the contribution type on the submission form. All submissions must use the Dagstuhl OASIcs template: https://submission.dagstuhl.de/documentation/authors#oasics
- Full paper: up to 10 pages, single column, excluding title page and references. Published in the proceedings.
- Short paper / experience report: up to 6 pages, single column, excluding title page and references. Published in the proceedings.
- Talk / demo: a 1–2 page extended abstract describing the talk or the demo setup. Reviewed for relevance and fit, featured in the program, not included in the proceedings.
Full papers and short papers undergo double-blind review; please remove author names, affiliations, and identifying acknowledgements from the manuscript.
PublicationPublication
Accepted full papers and short papers will be published open access in the HiPEAC Workshop proceedings by Schloss Dagstuhl, indexed in dblp and Scopus. Talk and demo contributions are featured in the program without an accompanying paper.
VenueVenue
The workshop is held in conjunction with the HiPEAC 2027 conference in Glasgow, Scotland, in January 2027. Workshop web page: https://edge-group-polito.github.io/OpenSoC4HE/
ContactContact
All questions about submissions should be emailed to opensoc4he@gmail.com

