ITC-Asia 2019: The 3rd International Test Conference in Asia Tokyo Denki University Tokyo, Japan, September 3-5, 2019 |
Conference website | http://www.itc-asia.info.hiroshima-cu.ac.jp/2019/ |
Submission link | https://easychair.org/conferences/?conf=itcasia2019 |
Abstract registration deadline | March 8, 2019 |
Submission deadline | March 8, 2019 |
With the test technology facing its grand challenges to ensure the quality of ICs and electronic systems incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet of Things, cloud computing, automotive electronics, etc., global proliferation and cooperation is increasingly more important. International Test Conference has been a flagship conference in test technology since 1970. With an attempt to stimulate more discussion and interaction between the academia and the industry around the globe, the 1st ITC-Asia was initiated in Taipei in 2017, and the 2nd ITC-Asia will be held in Harbin China in 2018. The 3rd ITC-Asia will be held in Tokyo Japan in 2019. Outstanding papers with extension will be invited to ITC 2019.
Submission Guidelines
Regular paper submissions should be made electronically by PDF manuscripts only, not exceeding 6 pages in IEEE 2-column format (including abstract, figures, tables, and bibliography). A submission will be considered evidence that upon acceptance at least one author will attend the conference to make the presentation. Authors of accepted papers are also responsible for preparing the final manuscripts in time to be included in the electronic proceeding. Conference content will be submitted for inclusion into IEEE Xplore as well as other Abstracting and Indexing (A&I) databases. At least one full registration to the conference is required for each accepted paper.
List of Topics
- Autonomous Testing
- Heterogeneous Testing
- Reliability and Testing for Approximate/Quantum Computing
- Hardware Oriented Security and Trust
- Design Validation and Debug
- ATE Design
- Analog and Mixed-Signal Test
- RF Test
- High-Speed I/O Test
- Fault Modeling and Simulation
- ATPG (Automatic Test Pattern Generation)
- Design for Testability
- Built-In Self-Test
- Delay Test
- System-on-Chip Test
- Test Compression
- Power-Aware and/or Thermal-Aware Test
- Memory Test, Diagnosis, and Repair
- Fault Diagnosis and Failure Analysis
- Yield Analysis and Learning
- Safety and Test for Automotive ICs
- Test for Internet of Things
- Test for Emerging Devices
- CPU/GPU Test
- MEMS/Sensor Test
- Online Test
- On-Chip Measurement
- SiP, 2.5D, and 3D IC Test
- Interconnect Test
- Board-Level Testing and Diagnosis
- Test Standards
- Test Economics
- Reliability Issues
- Fault Tolerance
- Test for Reconfigurable Systems
- Software Test and Reliability
- Dependable Systems and Networks
Committees
Program Committee
Organizing committee
- General Co-Chairs:
- Tomoo INOUE (Hiroshima City Univ.)
- Seiji KAJIHARA (Kyushu Institute of Technology)
- Program Co-Chairs:
- Hideyuki ICHIHARA (Hiroshima City Univ.)
- Masahiro ISHIDA (ADVANTEST Corp.)
- Finance Chair:
- Masayuki ARAI (Nihon Univ.)
- Local Arrangement Chair:
- Satoshi KOMATSU (Tokyo Denki Univ.)
- Industry Co-Chairs:
- Shuji HAMADA (Socionext Inc.)
- Tutorial Co-Chairs:
- Satoshi Ohtake (Oita Univ.)
- Registration Chair:
- Michihiro SHINTANI (NAIST)
- Publication Chair:
- Yousuke MIYAKE (Kyushu Institute of Technology)
- Publicity Chair:
- Senling WANG (Ehime Univ.)
- Secretary:
- Kohei MIYASE (Kyushu Institute of Technology)
Contact
Program Co-Chairs: Hideyuki ICHIHARA and Masahiro ISHIDA
E-mail: pc2019 <at> itc-asia.info.hiroshima-cu.ac.jp