The First Workshop on Computer Architecture Research with RISC-V (CARRV) brings together researchers in fields related to computer architecture, compilers, and systems for technical exchange on using RISC-V in computer architecture research.  Submission of early work is encouraged. The topics of specific interest for the workshop include, but are not limited to:

• RISC-V simulation/emulation infrastructures, including ports of existing infrastructures
• Easily modifiable RISC-V RTL cores to support research
• Whole-SoC simulators/emulators and/or models built around RISC-V
• RISC-V-based research prototypes
• Machine-readable formal models and verification methodologies
• Compiler toolchains and operating system ports to support systems research
• Security architecture research
• Memory model research
• Quantitative comparison of RISC-V with other ISAs

The workshop is intended to be highly interactive with an open session discussing experiences with using the current state of the RISC-V ecosystem for architecture research and what directions to take to improve it.

Important Dates

Abstract submission deadline: August 1, 2017 August 8, 2017

Full paper submission deadline: August 8, 2017 August 15, 2017

Author notification: August 31, 2017

Camera-ready version due: September 14, 2017

Submission Guidelines

All papers should be submitted electronically by EasyChair. Submissions must be limited to 6 pages including figures and tables, plus as many pages as needed for references.. Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here.

Contact

All questions about submissions can be emailed to Arun Thomas <arun.thomas@baesystems.com>.