secriscv'22: 2022 International Workshop on Secure RISC-V Architecture Design Exploration Embedded Systems Week (ESWEEK) Phoenix, AZ, United States, October 13-14, 2022 |
Conference website | https://secriscv.org/ |
Submission link | https://easychair.org/conferences/?conf=secriscv22 |
Abstract registration deadline | August 26, 2022 |
Submission deadline | September 2, 2022 |
Submission Guidelines
Following the very successful and well-attended SECRISC-V’20 and SECRISC-V’21, the Secure RISC-V (SECRISC-V) Architecture Design Exploration Workshop seeks original research papers on the design, implementation, verification, and evaluation of micro-architecture security features, hardware-assisted security techniques, and secure executions around the RISC-V instruction set architecture (ISA).
The Workshop will serve as the anchor to the in-person portion of the ESWEEK in Phoenix, Arizona, Thursday October 13th to Friday October 14th, 2022.
The Theme for this year’s workshop is Secure RISC-V for the Embedded World.
Submission Format
- Oral Presentation Submission: The paper must be submitted in PDF format. The content of the submission is limited to four (4) pages - 8.5"x11" in standard IEEE two-column format (both blind and non-blind submission forms are accepted).
- Poster Submission: Title and abstract - must be submitted in PDF format.
Website: https://secriscv.org/
List of Topics
Submission of early work is encouraged. The RISC-V ISA based topics of specific interest for the workshop include, but are not limited to:
- Secure cores and multicores
- ISA extensions for Security
- Software and hardware obfuscation Techniques
- Hardware security solutions for machine learning
- Secure design for emerging applications: IoT, robotics, wearable computing, etc.
- Architectural designs and hardware security solutions for HPC, Data Centers and cloud computing
- Hardware virtualization and isolation for security
- Hardware-Software co-design solutions: graph analytics,
- Post-quantum cryptosystem designs
- Neuromorphic Architectures
- Blockchain enabled secure computing
- Classic and Modern encryption algorithms and hardware support
- Hardware security support for integrity and authentication, key distribution and management, and trust platform modules
- Secure execution environment
- Memory subsystem organization to secure data accesses
- Network-on-Chip (NoC) security feature to process and compute isolation
Organizing & Program Committee
- Michel A. Kinsy, Workshop Chair & Organizer, Secure, Trusted, and Assured Microelectronics (STAM) Center, Arizona State University
- Lake Bu, Charles Stark Draper Laboratory
- Kurt L. Keville, Massachusetts Institute of Technology (MIT)
- Alan Ehret, Secure, Trusted, and Assured Microelectronics(STAM) Center, Arizona State University
- Mihailo Isakov, Secure, Trusted, and Assured Microelectronics(STAM) Center, Arizona State University
- Xinfei Guo, Michigan University - Shanghai Jiao Tong University
- Jasmine A. Jones, Harvard University
- Donato Kava, Massachusetts Institute of Technology
Contact
All questions about submissions should be emailed to secriscv@gmail.com.