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NoCArc 2018

http://www.nocarc.org

11th International Workshop on Network on Chip Architectures

October 20, 2018 - Fukuoka, Japan
(To be held in conjunction with IEEE/ACM MICRO-51)
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G E N E R A L  I N F O R M A T I O N

With an advancement in both computing architectures and process technology, many-core architectures are going to have hundreds of cores into a single chip.  It is expected that the integration become in the order of thousand cores within 2020 as stated by the International Technology Roadmap for Semiconductors, which benefits some emerging applications such as machine learning engine design. By increasing the number of processing elements (PEs) in System-on-Chip (SoC), there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip. Techniques and architectures are needed for efficiently design and optimize NoC and evaluate it at the network or system level. NoCs are also prone to failure where techniques are required to tolerate, verify and test. In addition, new technologies are emerging as wireless, optical, and RF and for 2.5D and 3D packages.

The goal of NoCArc is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks. 
 

A R E A S  O F  I N T E R E S T

The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation
  * Topologies, routing, flow control
  * Managing QoS
  * Timing, synchronous/asynchronous communication
  * Reliability issues
  * Design methodologies and tools
  * Signaling & circuit design for NoC links

NoC Analysis and Verification
  * Power, energy and thermal issues
  * Benchmarking and experience with NoC-based systems
  * Modeling, simulation, and synthesis
  * Verification, debug and test
  * Metrics and benchmarks

Intelligent NoC Systems
  * Mapping of applications onto NoCs
  * NoC case studies, application-specific NoC design
  * NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
  * Machine learning for NoC and NoC-based Systems

On-Chip Communication Optimization
  * Communication efficient algorithms
  * Multi/many-core communication workload characterization and
    evaluation
  * Energy efficient NoCs and energy minimization 

NoC at System-level
  * Design of memory subsystem
  * NoC support for memory and cache access
  * OS support for NoCs
  * Programming models including shared memory, message passing and
    novel programming models
  * Issues related to large-scale systems (datacenters, supercomputers)
    with NoC-based systems as building blocks

Emerging NoC Technologies
  * Wireless, Optical, and RF
  * NoCs for 3D and 2.5D packages

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.
 

S U B M I S S I O N

Both research and application-oriented papers are welcome.  All papers should be submitted electronically by EasyChair. Submissions must be limited to 6 pages. Please, visit the workshop webpage (http://www.nocarc.org) for additional information about the submission process.


I M P O R T A N T  D A T E S

* Abstract submission deadline: July 25, 2018
* Paper submission deadline:    August 1, 2018
* Acceptance notification:         September 1, 2018
* Camera-ready version due:    September 8, 2018
* NoCArc workshop:                 October 20, 2018
 

O R G A N I Z E R S

STEERING COMMITTEE

* Maurizio Palesi, Univ. of Catania, Italy
* Davide Patti, Univ. of Catania, Italy
* Masoud Daneshtalab, MDH and KTH, Sweden
* Xiaohang Wang, South China University of Technology, China

GENERAL CHAIRS

* Masoumeh Ebrahimi, Univ. of Turku, Finland

TPC CHAIRS

* Kun-Chih (Jimmy) Chen, National Sun Yat-sen University, Taiwan
* Midia Reshadi, Science and research branch of Islamic Azad University