ITC-Asia 2020: The 4th International Test Conference in Asia TWTC Nangang Exhibition Hall Taipei, Taiwan, September 23-25, 2020 |
Conference website | http://sscas.ee.ncku.edu.tw/ITC-Asia-2020/ |
Submission link | https://easychair.org/conferences/?conf=itcasia2020 |
Abstract registration deadline | March 16, 2020 |
Submission deadline | March 23, 2020 |
With the test technology facing its grand challenges to ensure the quality, safety, and security of today’s ICs and electronic systems incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet of Things, cloud computing, automotive electronics, etc., global proliferation and cooperation has grown increasingly even more important. International Test Conference has been a flagship conference in test technology since 1970. With an attempt to stimulate more discussion and interaction between the academia and the industry around the globe, ITC-Asia was initiated as a sister conf. of ITC in 2017. This year, it is again co-located with SEMICON Taiwan in Taipei city. Welcome to join us to immerse ourselves in not only the state-of-the-art test technology, but also numerous semiconductor industry forums organized by SEMICON Taiwan.
Submission Guidelines
Regular paper submissions should be made electronically by PDF manuscripts only, not exceeding 6 pages in IEEE 2-column format (including abstract, figures, tables, and bibliography). A submission will be considered evidence that upon acceptance at least one author will attend the conference to make the presentation. Authors of accepted papers are also responsible for preparing the final manuscripts in time to be included in the electronic proceedings, which will eventually be published in IEEE Xplore Digital Library. At least one full registration to the conference is required for each accepted paper.
List of Topics
- Analog and Mixed-Signal Test
- ATE Design
- ATPG (Automatic Test Pattern Generation)
- Automotive IC Test
- Board-Level Testing and Diagnosis
- Built-In Self-Test for Logic Circuits
- CPU/GPU Test
- Delay Test
- Design for Testability for Logic Circuits
- Design Validation and Debug
- Fault Diagnosis and Failure Analysis
- Fault Modeling and Simulation
- Fault Tolerance
- Hardware Oriented Security and Thrust
- High-Speed I/O Test
- Interconnect Test
- Memory Test, Diagnosis, and Repair
- MEMS Test
- On-Chip Measurement
- Online Test
- Power-Aware and/or Thermal-Aware Test
- Reconfigurable System Test
- Reliability Issues
- RF Test
- Sensor Test
- SiP, 2.5D, and 3D IC Test
- System-on-Chip Test
- Test Compression
- Test Economics
- Test Methods for Low-Power Circuits
- Test Methods for Emerging Devices
- Test Methods for Internet of Things
- Test Standards
- Yield Analysis and Learning
Committees
Steering Committee Members
- Kuen-Jong Lee (Chair), National Cheng-Kung Univ.
- Tomoo Inoue, Hiroshima City Univ.
- Xiaowei Li, Chinese Academy of Sciences
- Li-C. Wang, U. of California, Santa Barbara
- Cheng-Wen Wu, National Tsing Hua Univ.
- Yervant Zorian, Synopsys
Organizing committee
- Shi-Yu Huang, General Chair, National Tsing Hua Univ.
- Soon-Jyh Chang, Technical Program Chair, National Cheng Kung Univ.
- Min-Der Hsieh, Finance Chair, National Cheng Kung Univ.
- Jiun-Lang Huang, National Taiwan Univ., Publications Chair
- Hsin-Wen Ting, Publicity Chair, National Kaohsiung Univ. of Science and Technology
- Hung-Pin (Charles) Wen, Tutorials Chair, National Chiao Tung Univ.
- Wen Lu, Local Arrangements Chair, SEMI Taiwan
- Harry Chen, Industry Sessions Chair, MediaTek Inc.
- Terry Tsao, Exhibitions Chair, SEMI Taiwan
- Krishnendu Chakrabarty, US Liaison, Duke University
- Ilian Polian, Europe Liaison, Stuttgart University
- Jennifer Dworak, ITC Liaison, Consultant
Venue
The conference will be held in TWTC Nangang Exhibition Hall, Taipei City, Taiwan
Contact
All questions about submissions should be emailed to Soon-Jyh Chang (Technical Program Chair), e-mail address: soon@mail.ncku.edu.tw