The 3D & Chiplet TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs, including systems-in-package (SiP), package-on-package (PoP), 3D-Stacks based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing and repairing such products. The 3D & Chiplet TEST Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.

3D & Chiplet TEST will take place in conjunction with the International Test Conference (ITC)

Topic Areas – You are invited to participate and submit your contributions to the 3D & Chiplet TEST Workshop. The workshop’s areas of interest include (but are not limited to) the following topics:

• Defects due to Wafer Thinning
• DfT Architectures for 3D-SICs
• D2D PHY-based monitoring, test & repair
• EDA Design-to-Test Flow for 3D-SICs
• Fault Models & Failure Analysis for interconnects
• Fault-Tolerant Design for multi-die
• Handling and Testing Singulated Stacks
• HBM Base-die & DRAM stack test & repair
• Interposer Testing & Debugging
• Known-Good Die / Known-Good Stack
• Monitoring interconnect signal integrity

• Pre-, Mid-, and Post-Bond Testing
• Reliability of 3D-SICs
• Stacking Yield of Dies, Interconnects, Redundancy & Repair
• Standards for 3D Testing, incl. IEEE P3405, stnd 1838
• Standards for test description 3dBlox
• Test Cost Modelling for 3D Packages
• Test Flow Optimization for 3D Packages
• Tester Architecture incl. ATE and BIST
• TSV-based lane test & repair
• UCie-based Multi-Die Test & Debug
• Wafer Probing and Probe Marks of 3D-SICs

Submission Instructions – Submissions must be sent as PDF files. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop’s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results.

Publications – 3D & Chiplet TEST focuses on early information sharing and free discussions; therefore, the workshop will not publish formal proceedings. Instead, the workshop will make available to all its registered participants an electronic workshop digest, which includes all material that authors/presenters are willing to contribute in PDF format: abstract, paper, slides, posters, background material, etc. This will allow authors to be free in their choice to submit their workshop paper later to a formal (IEEE or otherwise) journal, leveraging the audience feedback and discussions on the paper presentation at the 3D & Chiplet TEST Workshop.

Key Dates & Deadlines:

Submission deadline: September 25, 2024

Notification: September 30, 2024

Camera-ready material: October 28, 2024

For further information please contact:

Yervant Zorian

General Chair zorian@synopsys.com

Saman Adam

Program Co-Chair samana@tsmc.com

Sreejit Chakravarty

Program Co-Chair schakravarty@amperecomputing.com