SASIMI 2018: THE 21ST WORKSHOP ON SYNTHESIS AND SYSTEM INTEGRATION OF MIXED INFORMATION TECHNOLOGIES

This page contains an index consisting of author-provided keywords.

1
1-out-of-N Single-track handshaking protocol	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
3
3D IC	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
3D integration	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
3D SoC	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
6
65-nm	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
A
A* algorithm	Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars
ACAP	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
acceleration	RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA
ADC	A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration
affine decomposition	A Method to Identify Affine Equivalence Classes of Logic Functions
affine transform	A Method to Identify Affine Equivalence Classes of Logic Functions
aging	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Analog emulator	Hardware Implementation of WDF-Based Analog Circuit Emulation
annealing	A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
Anti-counterfeiting	Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products
AOI22	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
application-adaptive	Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC
Approximate computing	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
Approximate full adder	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
artificial intelligence	A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
Asynchronous circuit	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
Asynchronous circuits	Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors
ATPG	Accelerating Deterministic Parallel Test Pattern Generation by Hiding Latency Among Multi-threads
auto-correlation	A Method to Identify Affine Equivalence Classes of Logic Functions
automated testbench	Applying Bayesian Network-Based Machine Learning to Regression Design Verification
automotive system	Differential Update of Automotive Control Device Firmware
B
Bayesian network	Applying Bayesian Network-Based Machine Learning to Regression Design Verification
bi-directional interconnection	Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars
big data	RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA
Biochip Architecture Design	Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips
Building Block Computation Systems	A Shared Memory Chip for Twin-Tower of Chips
C
Charge Recycling	A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line
Circuit optimization	A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation
CLIF to Verilog	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
clock mesh	Hybrid Cross Mesh Synthesis with Register Clustering
clock skew	Hybrid Cross Mesh Synthesis with Register Clustering Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability
clock tree	Hybrid Cross Mesh Synthesis with Register Clustering
Clustering	A Method of Layout Pattern Classification Using Clustering
CNN	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
collision mitigation	A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment
combinatorial optimization problem	A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
computer aided design	A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
Computer-Aided Diagnosis	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Constraint graph	A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation
constraint satisfaction problem	Relaxed Routing Problem with Constraint Satisfaction Problem
Convolutional Neural Network	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Convolutional neural networks	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
coverage-driven verification	Applying Bayesian Network-Based Machine Learning to Regression Design Verification
Cut Mask	LESAR: A Dynamic Line-End Spacing Aware Detailed Router
cyclic row-shift decomposition	Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions
D
Data Bus Architecture	A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line
Data Coding	A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line
debug	A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
Decision Diagrams	On Optimization Methods for Decision Diagrams to Represent Probabilities
decision tree	RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA
decomposable functions	Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions
decomposition chart	Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions
decoupling capacitor	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
deep learning	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
Delay insertion	A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation
delay locked loop	Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis
delay variation	Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability
Design Automation	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits Voltage-drop Aware Timing Analysis for Pessimism Design Constraint Prevention A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
design for manufacturability	MapReduce-Based Pattern Classification for Design Space Analysis
Detailed Routing	LESAR: A Dynamic Line-End Spacing Aware Detailed Router
Deterministic	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes
digital circuit	A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
Digital Microfluidic Biochip	Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips
distributed control	Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs
double modular redundancy	Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution
DRC violations	Learning to Predict DRC Violations During Placement
Dynamic Compaction	Accelerating Deterministic Parallel Test Pattern Generation by Hiding Latency Among Multi-threads
Dynamic reconfiguration	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
dynamic scheduling	Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs
dynamic sensitivity control	A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment
E
ECO	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
embedded system	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA Differential Update of Automotive Control Device Firmware
energy efficient	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
Energy harvesting	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
energy measurement	Measurement and Modeling of Quadcopter Energy with ROS
energy modeling	Measurement and Modeling of Quadcopter Energy with ROS
equivalence class	A Method to Identify Affine Equivalence Classes of Logic Functions
Error Analysis	On Optimization Methods for Decision Diagrams to Represent Probabilities
error diagnosis	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
error location set	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
EV modeling	Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
F
fast Fourier transform	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
fault injection attacks	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
Field Programmable	Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs)
field programmable gate arrays	Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors
firmware	A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems
firmware update	Differential Update of Automotive Control Device Firmware
fixed-stride-type FFT	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
flash memory	A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems
Flexible distance-based hashing	An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
floating point number arithmetic	Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
Flow Path	Placement of Reagents on Programmable Microfluidic Devices
FPGA	Hardware Implementation of WDF-Based Analog Circuit Emulation A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA Near-Data Processing for Genome Analysis Using Software-Controlled SSD RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
frequency dependence	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Full system	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes
functional decomposition	Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions
G
Gauss-Jordan eliminaion	Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
General-synchronous framework	A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation
Genome analysis	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
global routing	A Bus-Aware Global Router
Graph reduction	A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation
H
hardware	Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC
Hardware Security	A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Power Analysis Method for a Lightweight Cipher Midori
Hash Function	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
heavy ion	Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation
high-level synthesis	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
Hybrid Caching System	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits
I
IC Testing	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
IEEE802.11ax	A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment
index generation function	Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions
inductance	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
industrial vision system	An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems
Integer Linear Programming	A Method of Layout Pattern Classification Using Clustering
Integrated optical circuits	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Ising model	A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
L
Layout Pattern Classification	A Method of Layout Pattern Classification Using Clustering
Legacy Circuit	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
Lightweight cipher	Power Analysis Method for a Lightweight Cipher Midori
Line-End Spacing	LESAR: A Dynamic Line-End Spacing Aware Detailed Router
Linear transform	A Method to Identify Affine Equivalence Classes of Logic Functions
Loading Reagent	Placement of Reagents on Programmable Microfluidic Devices
Logic optimization	Node Merging for Threshold Logic Network Optimization
Look-Up Table	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
loop unrolling	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
Low power	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line
Low power design	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
LSI	Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution
LUT	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
M
machine learning	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA Applying Bayesian Network-Based Machine Learning to Regression Design Verification A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
MapReduce	MapReduce-Based Pattern Classification for Design Space Analysis
memory reduction	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA
memristor	A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
memristor crossbar	A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
Microfluidic	Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs)
Midori	Power Analysis Method for a Lightweight Cipher Midori
minimizing delay	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Minimum Maximum-Edge-Weight Matching	Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing
mixed structure	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
MLC	A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems
Modeling	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes
monotonic switching ADC	A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration
Motor control	Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
multi-input function	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Multi-Level Cache	A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization
multi-objective genetic algorithm	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Multi-Processor System-on-Chip	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
multiple receivers	Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers
Multiple-Patterning Lithography	LESAR: A Dynamic Line-End Spacing Aware Detailed Router
Multiplexer	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
Multiplier	Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits
mutual inductance	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
N
Nanophotonic devices	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
nanophotonics	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
NBTI	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs
Near-data processing	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
Near-threshold computing	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits
Nearest neighbor search	An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
negotiation-based router	Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars
Netlist Converter	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
neural network	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
neuromorphic computing	Performance Analysis of Temporal Codings for Spiking Neural Network
Node merging	Node Merging for Threshold Logic Network Optimization
nonvolatile resistive-change switch	Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars
O
one-hot representation	Relaxed Routing Problem with Constraint Satisfaction Problem
One-Pass Synthesis Flow	Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips
optical access network	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC
optical integrated circuit	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Optical Parallel Multiplier	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
output controll strategy	Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers
Output limit	Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
Oxygen Concentration Sensor	An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster
P
Parallelism	Accelerating Deterministic Parallel Test Pattern Generation by Hiding Latency Among Multi-threads Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
Parity Spacing	LESAR: A Dynamic Line-End Spacing Aware Detailed Router
parts counting	An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems
pattern classification	MapReduce-Based Pattern Classification for Design Space Analysis
Performance analysis	Performance Analysis of Temporal Codings for Spiking Neural Network A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes
physical design	A Bus-Aware Global Router
placement	Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors
placement and routing	Learning to Predict DRC Violations During Placement
post-silicon tuning	Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis
Power analysis	Power Analysis Method for a Lightweight Cipher Midori
power analysis attacks	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
power delivery network	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Power-gating	A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs
Processor and Memory Allocation	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
processors	Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors
programmable delay element	Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability
Programmable Microfluidic Devices	Placement of Reagents on Programmable Microfluidic Devices
programmble	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC
protocol-processing circuit	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC
pruning	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA
Prüfer encoding	MapReduce-Based Pattern Classification for Design Space Analysis
PUF	A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring
Q
quadcopters	Measurement and Modeling of Quadcopter Energy with ROS
R
radiation hardening	Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation
random forest	RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA
Reconfigurable structure	A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs
register clustering	Hybrid Cross Mesh Synthesis with Register Clustering
regression analysis	Measurement and Modeling of Quadcopter Energy with ROS
relaxed routing problem	Relaxed Routing Problem with Constraint Satisfaction Problem
reliability	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Represent Probabilities	On Optimization Methods for Decision Diagrams to Represent Probabilities
Reuse Distance	A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization
Ring Oscillator	A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring
ROS	Measurement and Modeling of Quadcopter Energy with ROS
routing	A Bus-Aware Global Router
RSA cryptosystem	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
RSF	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
RSFQ circuits	Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits
RSM	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
RTL verification	Applying Bayesian Network-Based Machine Learning to Regression Design Verification
RTOS	Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC
S
safety	Differential Update of Automotive Control Device Firmware
SAR-ADC	A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration
scheduling	Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution
schematic	A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
security	Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products Differential Update of Automotive Control Device Firmware
Set-Pair Routing	Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing
Shared memory	A Shared Memory Chip for Twin-Tower of Chips
side channel attack resistant design	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
single event transient	Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation
Single-ISA Heterogeneous Multi-core Architecture	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
SoC	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
soft error	Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation
Sparsity	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
spatial reuse	A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment
spectral transform	A Method to Identify Affine Equivalence Classes of Logic Functions
spiking neural network	Performance Analysis of Temporal Codings for Spiking Neural Network
SRAM	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits
SSD	Near-Data Processing for Genome Analysis Using Software-Controlled SSD A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems
Standard-Cell Memory (SCM)	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits
state machine	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC
Stochastic Computing	Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits
Strassen's algorithm	Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
subsampling	RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA
Support Vector Machine	Learning to Predict DRC Violations During Placement Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
System Level Design	A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization
T
Tamper resistance	Power Analysis Method for a Lightweight Cipher Midori
Target Pin-Pair	Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing
tcad simulation	Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation
TCI	A Shared Memory Chip for Twin-Tower of Chips
Test Time	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
Testing	Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs)
thermal analysis	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
thermal management	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
thermo-mechanical stress	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Threshold logic	Node Merging for Threshold Logic Network Optimization
Through Silicon Vias	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
timing	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
Timing Analysis	Voltage-drop Aware Timing Analysis for Pessimism Design Constraint Prevention
timing correction	Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability
Transmission-Gate	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
tree structure	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
U
unsatisfiable core	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
V
variable latency operations	Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs
Verification of authenticity	Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products
Virtual prototypes	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes
virtualization	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes
Voltage-drop	Voltage-drop Aware Timing Analysis for Pessimism Design Constraint Prevention
W
Wake-up scheduling	A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs
Walsh transform	A Method to Identify Affine Equivalence Classes of Logic Functions
Wave Digital Filter(WDF)	Hardware Implementation of WDF-Based Analog Circuit Emulation
Wired Communication	A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line
wireless power transfer (WPT)	Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers
Wireless Sensor Network	An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster
Wrapper Chain	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
Wrapper Optimization	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
writing speed	A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems
Z
ZigBee	An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster

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