Days: Monday, March 26th Tuesday, March 27th
View this program: with abstractssession overviewtalk overview
09:20 | Cyber-Physical Systems: Opportunities, Challenges, and (Some) Solutions ( abstract ) |
10:20 | A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes ( abstract ) |
10:22 | Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC ( abstract ) |
10:24 | Performance Analysis of Temporal Codings for Spiking Neural Network ( abstract ) |
10:26 | A Bus-Aware Global Router ( abstract ) |
10:28 | A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems ( abstract ) |
10:30 | A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring ( abstract ) |
10:32 | Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs ( abstract ) |
10:34 | Near-Data Processing for Genome Analysis Using Software-Controlled SSD ( abstract ) |
10:36 | Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits ( abstract ) |
10:38 | A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture ( abstract ) |
10:40 | A Carry-Predicting Full Adder for Accuracy-Scalable Computing ( abstract ) |
10:42 | A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits ( abstract ) |
10:44 | Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC ( abstract ) |
10:46 | Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions ( abstract ) |
10:48 | Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images ( abstract ) |
10:50 | An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster ( abstract ) |
10:52 | An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets ( abstract ) |
10:54 | A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization ( abstract ) |
13:30 | Heterogeneous Multi-Processor Pipelines: a Real-Time MPSoC Story ( abstract ) |
14:20 | Placement of Reagents on Programmable Microfluidic Devices ( abstract ) |
14:22 | An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters ( abstract ) |
14:24 | On Optimization Methods for Decision Diagrams to Represent Probabilities ( abstract ) |
14:26 | Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution ( abstract ) |
14:28 | An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems ( abstract ) |
14:30 | Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips ( abstract ) |
14:32 | A Deep Neural Network Based Approach to Achieve Aesthetic Schematics ( abstract ) |
14:34 | A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line ( abstract ) |
14:36 | Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication ( abstract ) |
14:38 | Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm ( abstract ) |
14:40 | Node Merging for Threshold Logic Network Optimization ( abstract ) |
14:42 | A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation ( abstract ) |
14:44 | High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit ( abstract ) |
14:46 | MapReduce-Based Pattern Classification for Design Space Analysis ( abstract ) |
14:48 | Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation ( abstract ) |
14:50 | Measurement and Modeling of Quadcopter Energy with ROS ( abstract ) |
14:52 | Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits ( abstract ) |
14:54 | Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products ( abstract ) |
“What is the next place to go, in the era of IoT and AI?”
Moderator:
Prof. Robert Dutton (Stanford University)
Panelist:
Prof. Peter Marwedel (Technische Universitat Dortmund)
Prof. Sri Parameswaran (University of New South Wales)
Prof. Elena Dubrova (Royal Institute of Technology)
Prof. Iris Hui-Ru Jiang (National Taiwan University)
Synopsis:
Wherever we go, we cannot avoid seeing these two terms: IoT and AI. Starting with short talks by experts in the domains related to synthesis and system integration, we will discuss, in the era of IoT and AI, what are challenges and pitfalls in those domains, and also directions we should go in the long run.
Organizer:
Prof. Kiyoharu Hamaguchi (Shimane University)
View this program: with abstractssession overviewtalk overview
09:10 | Lightweight Cryptographic Primitives for Resource-Constrained Devices ( abstract ) |
10:00 | Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks ( abstract ) |
10:02 | Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence ( abstract ) |
10:04 | A Method of Layout Pattern Classification Using Clustering ( abstract ) |
10:06 | A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs ( abstract ) |
10:08 | Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs) ( abstract ) |
10:10 | Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture ( abstract ) |
10:12 | Accelerating Deterministic Parallel Test Pattern Generation by Hiding Latency Among Multi-threads ( abstract ) |
10:14 | Learning to Predict DRC Violations During Placement ( abstract ) |
10:16 | Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability ( abstract ) |
10:18 | Differential Update of Automotive Control Device Firmware ( abstract ) |
10:20 | LESAR: A Dynamic Line-End Spacing Aware Detailed Router ( abstract ) |
10:22 | A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration ( abstract ) |
10:24 | Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint ( abstract ) |
10:26 | Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch ( abstract ) |
10:28 | Voltage-drop Aware Timing Analysis for Pessimism Design Constraint Prevention ( abstract ) |
10:30 | A Method to Identify Affine Equivalence Classes of Logic Functions ( abstract ) |
10:32 | Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers ( abstract ) |
10:34 | Relaxed Routing Problem with Constraint Satisfaction Problem ( abstract ) |
10:36 | Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing ( abstract ) |
13:20 | Timing is Everything! ( abstract ) |
14:10 | Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation ( abstract ) |
14:12 | Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform ( abstract ) |
14:14 | A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment ( abstract ) |
14:16 | A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA ( abstract ) |
14:18 | Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis ( abstract ) |
14:20 | A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies ( abstract ) |
14:22 | RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA ( abstract ) |
14:24 | Power Analysis Method for a Lightweight Cipher Midori ( abstract ) |
14:26 | Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing ( abstract ) |
14:28 | Hardware Implementation of WDF-Based Analog Circuit Emulation ( abstract ) |
14:30 | An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data ( abstract ) |
14:32 | A Shared Memory Chip for Twin-Tower of Chips ( abstract ) |
14:34 | Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC ( abstract ) |
14:36 | Hybrid Cross Mesh Synthesis with Register Clustering ( abstract ) |
14:38 | Applying Bayesian Network-Based Machine Learning to Regression Design Verification ( abstract ) |
14:40 | Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor ( abstract ) |
14:42 | Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars ( abstract ) |
14:44 | Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors ( abstract ) |
14:46 | Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction ( abstract ) |
16:00 | Time-Domain Neural Network for Deep Learning Inference ( abstract ) |