SASIMI 2018: THE 21ST WORKSHOP ON SYNTHESIS AND SYSTEM INTEGRATION OF MIXED INFORMATION TECHNOLOGIES

A
Abe, Kodai	On Optimization Methods for Decision Diagrams to Represent Probabilities
Abe, Tomoki	Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
Akagi, Kano	Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing
Amano, Hideharu	A Shared Memory Chip for Twin-Tower of Chips
Ando, Kota	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Ando, Naoki	A Shared Memory Chip for Twin-Tower of Chips
Arai, Yuki	A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation
Asai, Tetsuya	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
B
Baba, Hiroyuki	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
Bian, Song	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring
Butler, Jon T.	Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions
C
Chang, Hao-Yu	Hardware Implementation of WDF-Based Analog Circuit Emulation
Chang, Jia-Heng	A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration
Chang, Wen-Wei	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
Chang, Yi-Hsiang	MapReduce-Based Pattern Classification for Design Space Analysis
Chen, Bo-Yuan	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
Chen, Chi-Kang	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization
Chen, Hung-Ming	Learning to Predict DRC Violations During Placement
Chen, Li-Chin	Learning to Predict DRC Violations During Placement
Chen, Yi-Jung	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
Chen, Yu-Guang	A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs
Chen, Yung-Chih	Node Merging for Threshold Logic Network Optimization
Cheng, Wei-Kai	Hybrid Cross Mesh Synthesis with Register Clustering
Chiu, Kun-Wei	A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs
D
Dubrova, Elena	Lightweight Cryptographic Primitives for Resource-Constrained Devices Cyber-Physical Systems: Opportunities, Challenges, and (Some) Solutions Timing is Everything! Heterogeneous Multi-Processor Pipelines: a Real-Time MPSoC Story Time-Domain Neural Network for Deep Learning Inference
E
Egawa, Takumi	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
F
Fuchi, Shingo	Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products
Fujii, Haruya	Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
Fujii, Tomoya	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA
Fujikawa, Masaki	Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products
Fujimoto, Tetsuaki	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
Fujiyoshi, Kunihiro	A Method of Layout Pattern Classification Using Clustering
Fukui, Masahiro	Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
Furumi, Kaoru	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Furumi, Kaoru	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Furushima, Jukiya	Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors
G
Guo, Da-Yi	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes
Gupta, Ankur	Placement of Reagents on Programmable Microfluidic Devices
Gyoten, Hidenori	A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
H
Hachiya, Koutaro	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Hamaguchi, Kiyoharu	Applying Bayesian Network-Based Machine Learning to Regression Design Verification
Haneda, Kentaro	On Optimization Methods for Decision Diagrams to Represent Probabilities
Hanyu, Takahiro	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
Hara, Daiki	A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line
Hasegawa, Mitsuru	A Method of Layout Pattern Classification Using Clustering
Hasegawa, Takashi	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
Hatanaka, Masahide	A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment
Hatta, Saki	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC
Hiromoto, Masayuki	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
Hirose, Kazutoshi	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Hirose, Tetsuya	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
Ho, Tsung-Yi	Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs)
Hong, Hao-Chiao	A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems
Hoshide, Akito	An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster
Hosomi, Takeo	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
Hsieh, Yi-Cheng	A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration
Hsu, Hsin-Ju	Hardware Implementation of WDF-Based Analog Circuit Emulation
Huang, Juinn-Dar	Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips
Huang, Shih-Hsu	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
Hung, Chung-Chih	A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration
I
Ichikawa, Kouji	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
Iguchi, Yukihiro	A Method to Identify Affine Equivalence Classes of Logic Functions
Ikebe, Masayuki	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Ikeshita, Takahiro	Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
Imagawa, Takashi	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars
Imai, Masashi	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
Imai, Masashi	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Imai, Masashi	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Imai, Yuuki	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Inagi, Masato	An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
Inoue, Hiroaki	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
Inoue, Masahiro	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
Ishihara, Tohru	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Ishihara, Tohru	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Ishihara, Yuto	Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution
Ishino, Shuhei	A Method of Layout Pattern Classification Using Clustering
Ishiura, Nagisa	Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
Ito, Kazuhito	Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution
Ito, Kenshi	Performance Analysis of Temporal Codings for Spiking Neural Network
Ito, Soichiro	Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers
Ito, Toshitaka	An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
Itotani, Yuri	An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
J
Jou, Jing-Yang	Hardware Implementation of WDF-Based Analog Circuit Emulation
K
Kakiuchi, Yosuke	Applying Bayesian Network-Based Machine Learning to Regression Design Verification
Kanamoto, Toshiki	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Kanamoto, Toshiki	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
Kanamoto, Toshiki	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Kaneda, Kazufumi	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Kaneko, Mineo	Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability
Katayama, Naoki	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
Katsumata, Kazuho	Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability
Kazama, Satoshi	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
Kimura, Shinji	RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA
Kita, Shota	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Kita, Shota	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Kito, Nobutaka	Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits
Kobayashi, Yuki	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
Koide, Tetsushi	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Kojima, Takuya	A Shared Memory Chip for Twin-Tower of Chips
Koketsu, Yurie	Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits
Kubo, Taisei	Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis
Kuo, Chun-Chia	Voltage-drop Aware Timing Analysis for Pessimism Design Constraint Prevention
Kurokawa, Atsushi	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Kuroki, Nobutaka	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
Kuwamura, Shinya	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
L
Lei, Ping	RF-SM: Random Forest Training Process Acceleration with Subsampling Method on FPGA
Li, Yih-Lang	LESAR: A Dynamic Line-End Spacing Aware Detailed Router MapReduce-Based Pattern Classification for Design Space Analysis
Liao, Pin-Xin	A Bus-Aware Global Router
Lin, Dave Y.-W.	Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation
Lin, Ing-Chao	A Novel NBTI-Aware Wake-up Strategy for Power-Gated Designs
Lin, Lei	Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
Lin, Louis Y.-Z.	Accelerating Deterministic Parallel Test Pattern Generation by Hiding Latency Among Multi-threads
Liu, Bo	An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis
Liu, Chia-Hung	Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips
Liu, Chia-Yin	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
Liu, Chien-Nan Jimmy	Hardware Implementation of WDF-Based Analog Circuit Emulation
Liu, Chunfeng	Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs)
Liu, Jin	A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment
Liu, Loo Shean	Hardware Implementation of WDF-Based Analog Circuit Emulation
Liu, Yi-Yu	Voltage-drop Aware Timing Analysis for Pessimism Design Constraint Prevention
M
Maekawa, Kotaro	Measurement and Modeling of Quadcopter Energy with ROS
Maruyama, Satoru	Placement of Reagents on Programmable Microfluidic Devices
Matsumoto, Shogo	A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
Matsushita, Yusuke	A Shared Memory Chip for Twin-Tower of Chips
Matsuura, Kyu	A Method to Identify Affine Equivalence Classes of Logic Functions
Mieno, Hiroshi	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Miyanaga, Yoshikazu	Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
Miyauchi, Tetsuo	Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC
Miyoshi, Takashi	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
Morita, Shumpei	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Motomura, Masato	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
N
Nagaoka, Yuta	Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation
Nagayama, Shinobu	An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
Nakahara, Hiroki	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA
Nakamura, Makoto	An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems
Nakano, Wakako	Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs
Nakatake, Shigetoshi	An Implementation of Low-cost Wireless Sensor Network for Wide-area Disaster Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis
Namiki, Mitaro	A Shared Memory Chip for Twin-Tower of Chips
Negoro, Shunsuke	Measurement and Modeling of Quadcopter Energy with ROS
Nishizawa, Shinichi	Minimization of Equality Check for Soft Error Detection in DMR Design Implemented with Error Correction by Operation Re-execution
Noguchi, Yasuo	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
Notomi, Masaya	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Notomi, Masaya	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Nozaki, Kengo	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Nozaki, Kengo	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Nozaki, Yusuke	Power Analysis Method for a Lightweight Cipher Midori
Numa, Masahiro	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
O
Ochi, Hiroyuki	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars
Ogawa, Junji	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
Oh, Junghoon	Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability
Ohmura, Shogo	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
Okamoto, Shintaro	Impact of Distributing 3D Stacked ICs on Maximum Temperature Reduction
Okamoto, Takumi	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Okuhara, Hayate	A Shared Memory Chip for Twin-Tower of Chips
Okura, Tetsuro	A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
Onizawa, Naoya	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
Onodera, Hidetoshi	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Onodera, Hidetoshi	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Onoye, Takao	A Collision Mitigation Method on Spatial Reuse for WLAN in a Dense Residential Environment An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems
Osako, Naoki	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
Ota, Sayuri	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
Otake, Tatsuki	Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors
R
Raytchev, Bisser	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Roy, Sudip	Placement of Reagents on Programmable Microfluidic Devices
S
Saito, Hiroshi	Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors
Sakamoto, Takeshi	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC
Sakata, Kazuyuki	Prediction of the Impact of Mutual Inductance on Timing Towards Nano-scale SoC
Samanta, Radhamanjari	LESAR: A Dynamic Line-End Spacing Aware Detailed Router
Sasao, Tsutomu	A Method to Identify Affine Equivalence Classes of Logic Functions Analysis of Cyclic Row-Shift Decompositions for Index Generation Functions Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
Sato, Shimpei	A Design Algorithm for a Neuron Pruning Toward a Compact Binarized Deep Convolution Neural Network on an FPGA Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing
Sato, Takashi	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture
Sato, Toshinori	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
Satomi, Yuuta	Power Delivery Network Optimization of 3D ICs Using Multi-Objective Genetic Algorithm
Shibata, Atsuya	Measurement and Modeling of Quadcopter Energy with ROS
Shibata, Seiya	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
Shin, Zuitoku	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Shintani, Michihiro	Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Shinya, Akihiko	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Shinya, Akihiko	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Shiomi, Jun	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits
Sombatsiri, Salita	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
Su, Chung-Cheng	A 12-bit 10MS/s SAR ADC with Mixed Switching and Background Offset Calibration
Su, Hong-Yan	LESAR: A Dynamic Line-End Spacing Aware Detailed Router MapReduce-Based Pattern Classification for Design Space Analysis
Sukezane, Daichi	Measurement and Modeling of Quadcopter Energy with ROS
Syafalni, Infall	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
T
Tajima, Kaori	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
Takagi, Kazuyoshi	Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits
Takahashi, Atsushi	Target Pin-Pair Selection Algorithm Using Minimum Maximum-Edge-Weight Matching for Set-Pair Routing
Takahashi, Wataru	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
Takakura, Ryosuke	Applying Bayesian Network-Based Machine Learning to Regression Design Verification
Takamaeda-Yamazaki, Shinya	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Takashima, Yasuhiro	Relaxed Routing Problem with Constraint Satisfaction Problem Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis
Takata, Kenta	A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies
Takata, Kenta	An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters
Takayama, Kouki	Anti-counterfeiting and Authenticity Verification Technique for Molded Synthetic Resin Products
Takenaka, Takashi	Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks
Takeuchi, Yoshinori	Performance Analysis of Temporal Codings for Spiking Neural Network
Takezaki, Ayano	An Error Diagnosis Technique Based on Unsatisfiable Cores to Extract Error Locations Sets
Tamaki, Toru	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Tanaka, Kiyofumi	Building a Framework for an Application-Adaptive Processor System on FPGA-based SoC
Tanaka, Nobuyuki	Area-efficient Programmable Finite-state Machine Toward Next Generation Access Network SoC
Tanaka, Shinji	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Tanaka, Yuki	A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring
Taniguchi, Ittetsu	An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems Measurement and Modeling of Quadcopter Energy with ROS
Tanimoto, Tadaaki	Differential Update of Automotive Control Device Firmware
Terashima, Sayaka	A Shared Memory Chip for Twin-Tower of Chips
Tomiyama, Hiroyuki	Measurement and Modeling of Quadcopter Energy with ROS
Topaloglu, Rasit Onur	MapReduce-Based Pattern Classification for Design Space Analysis
Tsai, Cheng-Lin	A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization
Tsai, Ming-Ying	Processor and Memory Co-Allocation for MPSoCs with Single-ISA Heterogeneous Multi-Core Architecture
Tsay, Ren-Song	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization
Tsuchida, Yoshiki	Development and Evaluation of a Magnetic Resonant Coupling Wireless Power Transfer System for Multiple Receivers Motor Modeling, and Simulation of the Driving Performance of an EV-cart with the Motor
Tsukiyama, Shuji	A Heuristic Method for Delay Insertion to Improve Clock Period of General-Synchronous Circuit and Its Evaluation
Tsutsui, Hiroshi	Hardware Design Exploration of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
U
Uematsu, Ryota	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Ueyoshi, Kodai	Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Ukezono, Tomoaki	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
W
Wakabayashi, Kazutoshi	Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
Wakabayashi, Shin'Ichi	An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data
Wakasugi, Katsuhiko	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
Wang, Ting-Chi	A Bus-Aware Global Router
Wei, Ying-Chi	LESAR: A Dynamic Line-End Spacing Aware Detailed Router
Wen, Charles H.-P.	Accelerating Deterministic Parallel Test Pattern Generation by Hiding Latency Among Multi-threads Radiation-Hardened Design by Delay-Controllable Flip-Flops for Soft-Error-Rate Mitigation
Wen, Xiaoqing	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
Wong, Fu-Lian	Node Merging for Threshold Logic Network Optimization
Wu, Hsin-I	A Highly Efficient Virtualization-Assisted Approach for Full-System Virtual Prototypes A Reuse-Distance Based Approach for Early-Stage Multi-level Cache Design Optimization
Wu, Yan-Shiun	MapReduce-Based Pattern Classification for Design Space Analysis
Wu, Yu-Yi	Test Wrapper Chain Design for Three-Dimensional SoCs under TSV Count Constraint
X
Xu, Hongjie	A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits
Y
Yamaguchi, Kosei	Routing Method Considering Programming Constraint of Reconfigurable Device Using Via-switch Crossbars
Yamaguchi, Saki	Relaxed Routing Problem with Constraint Satisfaction Problem
Yamashita, Shigeru	Placement of Reagents on Programmable Microfluidic Devices On Optimization Methods for Decision Diagrams to Represent Probabilities
Yamauchi, Takuya	A Deep Neural Network Based Approach to Achieve Aesthetic Schematics
Yang, Chih-Ko	A Firmware for Improving the Writing Performance of Multi-Chip MLC NAND Flash Memory Systems
Yang, Tongxin	Netlist Conversion from Customer Logic Interface Format (CLIF) to Verilog for Legacy Circuits
Yang, Tongxin	A Carry-Predicting Full Adder for Accuracy-Scalable Computing
Yang, Wei-Hao	Versatile Ring-Based Architecture for General-Purpose Digital Microfluidic Biochips
Yeh, Zih-Ming	Hybrid Cross Mesh Synthesis with Register Clustering
Yoneda, Tomohiro	Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing
Yoshida, Eiji	Near-Data Processing for Genome Analysis Using Software-Controlled SSD
Yoshida, Shigeto	Investigation of Real-Time Computer-Aided Diagnosis system using CNN feature and SVM identifier with Colorectal Endoscopic Images
Yoshikawa, Masaya	Power Analysis Method for a Lightweight Cipher Midori
Yoshikawa, Takefumi	A Low Power Data Bus Architecture by Charge Recycling Utilization on Single-Ended Transmission Line
Yura, Suguru	High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit
Z
Zang, Xuechen	Post-silicon Skew Tuning by Programmable Delay Element with Variability Analysis
Zhao, Qiaochu	An Efficient Parts Counting Method based on Intensity Distribution Analysis for Industrial Vision Systems
Zheng, Li-Cheng	Node Merging for Threshold Logic Network Optimization

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