Globalization of integrated circuits manufacturing has led to increased security concerns, notably IP theft. In response, many logic locking techniques have been developed for protecting designs, but many of these locking techniques have been shown to be vulnerable to SAT attacks. In this paper, we explore the use of Boolean sensitivity to analyze circuits locked with these techniques. We show that in typical circuits there is an inverse relationship between input width and sensitivity. We then demonstrate the utility of this relationship for deobfuscating circuits locked with a class of ``provably secure'' logic locking techniques. We conclude with an example of how to resist this attack, although the resistance is shown to be highly circuit dependent.