Verification testbenches are powerful tools when developing IC designs but are not always the most “welcoming” for non-verification engineers. When analog designers want to run certain blocks as transistors in a chip-level simulation, or test and evaluation teams want to gain vital insights to ensure their test setups are ready for day 1 of silicon on the bench, making the verification environment user friendly allows others access to this invaluable resource. For our teams, all that is required is knowledge of how to code in C/C++. For numerous projects, we have used a C++ based frontend to the UVM DV environment by utilizing the DPI feature of SystemVerilog.
In this paper, a description of DPI will be given, with an explanation of how the C++ frontend was implemented and the benefits it brought to our projects.