As aerospace and defense firms are working towards developing future air and space platforms, decisions involving which hardware and software elements to use in their design needs to be made. One significant design choice is the underlying instruction set architecture (ISA) that defines the interface between the software and hardware for a processor. A relatively new ISA called RISC-V has emerged as an open source alternative to commercial ISAs. Verifiable security, frozen base specification for long-term stability, designed for extensibility and no license fee for modifications makes RISC-V particularly well suited for aerospace and defense applications. In this work, we developed the system models of not only the RISC-V core but also the entire SoC where the RISC-V cores were plugged in. Using the system model, we are able to run target applications/benchmarks on RISC-V core and evaluate the performance and power for different clock frequencies, custom instructions, topology, cache associativity degrees, cache replacement policies, cache sizes, write back policies, bus width, buffer sizes, bus speeds, memory types, memory width, and interconnect protocols like the TileLink. For each of the simulation run, the model generates various statistics including details on pipeline stalls, execution unit utilization, buffer occupancy, cache accesses, number of evictions, write backs, throughput, cycles per instruction, memory latency and network latency. Performance and functional requirements were provided as input to the system model and faults were injected into the system model to determine the expected performance of the system under failure. Our SoC design was then updated to improve the fault tolerance and application performance by 30% under faults by adding redundant cores and error correction mechanisms, based on early results.