The field-programmable gate array (FPGA) vendors like Intel/Altera and AMD/Xilinx let designers create complex circuits by instantiating and interconnecting intellectual properties (IPs) from their provided tools like Vivado and Quartus [1,2]. The IPs are configurable and reusable by FPGA designs but not open to the simulators like Synopsys VCS, Cadence NC, and Mentor Graphic Modelsim/Questa. Therefore, this paper presents a binary design library including fundamental arithmetic circuits like full-adder, full-subtractor, binary multiplier, shifter, and more. The Chisel Hardware Construction Language (HCL) is employed to build the configurable designs, making each design module configurable with precisions including half-word, word, double-word, and quad-word. Chisel HCL is an open-source embedded domain-specific language which inherits the object-oriented and functional programming aspects of Scala for constructing hardware. Compared with traditional Verilog/VHLD Hardware Description Language (HDL), Chisel is scalable to the structural level of designs and suitable to the arithmetic implementations. Experimental results show the same accuracy with the Verilog HDL implementations. The hardware cost in terms of slice count, power consumption, and the maximum clock frequency is further presented in this research study.