Binary signed-digit (BSD) adders offer the ability to do addi- tion in constant time, independent of the operand width. This is done by allowing each digit to take three different values (one more then in stan- dard binary encoding), storing an arising carry bit at one position in the subsequent digit. Subsequently, this prevents carry propagation through- out the entire circuit. Previous work has evaluated one type of BSD adder encoding (BSD-SUM) regarding speedup to conventional adder architec- tures on logic synthesis level. This paper builds upon this work, extending it onto layout level for a more detailed view on area and power consumption overhead. We compare the BSD-SUM adder with three con- ventional binary adder architectures, namely Carry-Lookahead, Ripple- Carry circuits and the resulting circuitry of a + operator in HDL code and evaluate multiple typical operand widths. We found that the BSD- SUM adder architecture offers a area benefit over the Carry-Lookahead architecture for wide operand widths (64 bit and greater). We also found that the power consumption overhead of this architecture is quadratic when compared to binary adder architectures.