FLOC ON TUESDAY, JULY 22ND, 2014
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08:45-10:15 Session 156: VSL Keynote Talk
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Location: EI, EI 7 + EI 9, EI 10 + FH, Hörsaal 1
08:45 | VSL Keynote Talk: Verification of Computer Systems with Model Checking SPEAKER: Edmund Clarke ABSTRACT. Model Checking is an automatic verification technique for large state transition systems. The technique has been used successfully to debug complex computer hardware and communication protocols. Now, it is beginning to be used for complex hybrid (continuous/discrete) systems as well. The major disadvantage of the technique is a phenomenon called the State Explosion Problem. This problem is impossible to avoid in worst case. However, by using sophisticated data structures and clever search algorithms, it is now possible to verify hybrid systems with astronomical numbers of states. |
10:15-10:45Coffee Break
13:00-14:30Lunch Break
16:00-16:30Coffee Break
18:00-19:00 Session 157: SIGLOG Meeting (joint with VSL)
Location: FH, Hörsaal 8