SAT 2015: 18TH INTERNATIONAL CONFERENCE ON THEORY AND APPLICATIONS OF SATISFIABILITY TESTING

A
Alvarez, Mario M.	Towards Verification of Hybrid Systems in a Foundational Proof Assistant
Arcaini, Paolo	Formal validation and verification of a medical software critical component
Attie, Paul	Model and Program Repair via SAT Solving
B
Bartocci, Ezio	From Signal Temporal Logic to FPGA Monitors
Bastos, Joao	Modeling Resource Sharing using FSM-SADF
Beaumont, Jonny	Compositional design of asynchronous circuits from behavioural concepts
Bensalem, Saddek	Optimized Distributed Implementations of Timed Component-based Systems
Bonfanti, Silvia	Formal validation and verification of a medical software critical component
Bounov, Dimitar	C-To-Verilog Translation Validation
Brook, Alon	Local and Global Fairness in Concurrent Systems
C
Cao, Bingyi	Implementing Latency-Insensitive Dataflow Blocks
Chabot, Martial	Automatic and Configurable Instrumentation of C Programs with Temporal Assertion Checkers
Cherri, Ali	Model and Program Repair via SAT Solving
Combaz, Jacques	Optimized Distributed Implementations of Timed Component-based Systems
Corporaal, Henk	Modeling Resource Sharing using FSM-SADF
D
Dak Al Bab, Kinan	Model and Program Repair via SAT Solving
Dieudonne, Laurent	On the Deployment Problem of Embedded Systems
Dokhanchi, Adel	Metric Interval Temporal Logic Specification Elicitation and Debugging
Durand, William	Passive testing of production systems based on model inference
E
Eckardt, Horst	On the Deployment Problem of Embedded Systems
Edwards, Stephen A.	Implementing Latency-Insensitive Dataflow Blocks
F
Fainekos, Georgios	Metric Interval Temporal Logic Specification Elicitation and Debugging
Fujita, Masahiro	Logic analysis and optimization with quick identification of invariants through one time frame analysis
G
Ganty, Pierre	From Non-Zenoness Verification to Termination
Gargantini, Angelo	Formal validation and verification of a medical software critical component
Genaim, Samir	From Non-Zenoness Verification to Termination
Gerard, Leonard	Design and Verification of Multi-Rate Distributed Systems
Ghassabani, Elaheh	Hierarchical Multi-Formalism Proofs of Cyber Physical Systems
Gowda, Vignesh	Towards Verification of Hybrid Systems in a Foundational Proof Assistant
Greaves, David	Layering RTL, SAFL, Handel-C and Bluespec Constructs on Chisel HCL
Grosu, Radu	From Signal Temporal Logic to FPGA Monitors
H
Hannig, Frank	Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays
Heimdahl, Mats	Hierarchical Multi-Formalism Proofs of Cyber Physical Systems
Hoxha, Bardh	Metric Interval Temporal Logic Specification Elicitation and Debugging
J
Jacobs, Johan	Modeling Resource Sharing using FSM-SADF
Jaksic, Stefan	From Signal Temporal Logic to FPGA Monitors
Joosten, Sebastiaan	Process algebra semantics and reachability analysis for micro-architectural models of communication fabrics
Jouvelot, Pierre	Towards Refinement Types for Time-Dependent Data-Flow Networks
K
Kim, Martha A.	Implementing Latency-Insensitive Dataflow Blocks
Kloibhofer, Reinhard	From Signal Temporal Logic to FPGA Monitors
Kugele, Stefan	On the Deployment Problem of Embedded Systems
L
Lal, Ratan	From Non-Zenoness Verification to Termination
Lanik, Jan	Reducing power with activity trigger analysis
Lee, Insup	Hierarchical Multi-Formalism Proofs of Cyber Physical Systems
Legriel, Julien	Reducing power with activity trigger analysis
Lerner, Sorin	C-To-Verilog Translation Validation Towards Verification of Hybrid Systems in a Foundational Proof Assistant
Leung, Alan	C-To-Verilog Translation Validation
Li, Wenchao	Design and Verification of Multi-Rate Distributed Systems
Li, Xian	Verification Condition Generation for Hybrid Systems
M
Malecha, Gregory	Towards Verification of Hybrid Systems in a Foundational Proof Assistant
Maler, Oded	Reducing power with activity trigger analysis
Mashkoor, Atif	Formal validation and verification of a medical software critical component
Mazet, Kevin	Automatic and Configurable Instrumentation of C Programs with Temporal Assertion Checkers
Mendler, Michael	SCEst: Sequentially Constructive Esterel
Mokhov, Andrey	Compositional design of asynchronous circuits from behavioural concepts
Moore, Simon	A Generic Synthesisable Test Bench
Motika, Christian	SCEst: Sequentially Constructive Esterel
Murugesan, Anitha	Hierarchical Multi-Formalism Proofs of Cyber Physical Systems
N
Naylor, Matthew	A Generic Synthesisable Test Bench
Nguyen, Thang	From Signal Temporal Logic to FPGA Monitors
Nickovic, Dejan	From Signal Temporal Logic to FPGA Monitors
P
Peled, Doron	Local and Global Fairness in Concurrent Systems
Pierre, Laurence	Automatic and Configurable Instrumentation of C Programs with Temporal Assertion Checkers
Piriou, Erwan	Reducing power with activity trigger analysis
Popa, Ramona	On the Deployment Problem of Embedded Systems
Prabhakar, Pavithra	From Non-Zenoness Verification to Termination
Pucea, Gheorghe	On the Deployment Problem of Embedded Systems
R
Rahim, Fahim	Reducing power with activity trigger analysis
Rahim, Solaiman	Reducing power with activity trigger analysis
Rakib, Abdur	Modeling and verifying context-aware non-monotonic reasoning agents
Rathlev, Karsten	SCEst: Sequentially Constructive Esterel
Rayadurgam, Sanjai	Hierarchical Multi-Formalism Proofs of Cyber Physical Systems
Riccobene, Elvinia	Formal validation and verification of a medical software critical component
Ricketts, Daniel	Towards Verification of Hybrid Systems in a Foundational Proof Assistant
Ross, Kenneth A.	Implementing Latency-Insensitive Dataflow Blocks
S
Saklawi, Jad	Model and Program Repair via SAT Solving
Sakr, Mouhammad	Model and Program Repair via SAT Solving
Salva, Sébastien	Passive testing of production systems based on model inference
Schewe, Sven	Local and Global Fairness in Concurrent Systems
Schiffelers, Ramon	Modeling Resource Sharing using FSM-SADF
Schmaltz, Julien	Process algebra semantics and reachability analysis for micro-architectural models of communication fabrics
Schneider, Klaus	Verification Condition Generation for Hybrid Systems
Shankar, Natarajan	Design and Verification of Multi-Rate Distributed Systems
Shukla, Sandeep	Towards Refinement Types for Time-Dependent Data-Flow Networks
Smyth, Steven	SCEst: Sequentially Constructive Esterel
Sokolov, Danil	Compositional design of asynchronous circuits from behavioural concepts
Sokolsky, Oleg	Hierarchical Multi-Formalism Proofs of Cyber Physical Systems
Stuijk, Sander	Modeling Resource Sharing using FSM-SADF
T
Talpin, Jean-Pierre	Towards Refinement Types for Time-Dependent Data-Flow Networks
Tanase, Alexandru	Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays
Teich, Jürgen	Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays
Triki, Ahlem	Optimized Distributed Implementations of Timed Component-based Systems
U
Ul Haque, Hafiz Mahfooz	Modeling and verifying context-aware non-monotonic reasoning agents
V
Viaud, Emmanuel	Reducing power with activity trigger analysis
Voeten, Jeroen	Modeling Resource Sharing using FSM-SADF
Von Hanxleden, Reinhard	SCEst: Sequentially Constructive Esterel
W
Whalen, Michael	Hierarchical Multi-Formalism Proofs of Cyber Physical Systems
Witterauf, Michael	Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays
Wouda, Sanne	Process algebra semantics and reachability analysis for micro-architectural models of communication fabrics
Y
Yakovlev, Alex	Compositional design of asynchronous circuits from behavioural concepts

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