FMCAD 2020: FORMAL METHODS IN COMPUTER AIDED DESIGN
PROGRAM FOR WEDNESDAY, SEPTEMBER 23RD
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17:00-18:00 Session 8: Verification and Neural Networks
17:00
Selecting Stable Safe Configurations for Systems Modelled by Neural Networks with ReLU Activation

ABSTRACT. Techniques combining Machine Learning with Constraint Solving and Formal Methods have a wide range of safety critical applications. Our focus in this work is on analyzing Neural Networks with ReLU activation functions. We propose an algorithm for finding configurations of such networks that are safe and stable in a precise sense. We experimentally evaluate our algorithm on networks trained on real-life datasets originating from an industrial application.

17:15
Parallelization Techniques for Verifying Neural Networks

ABSTRACT. Inspired by recent successes with parallel techniques for solving Boolean satisfiability, we investigate a set of strategies and heuristics for leveraging parallelism to improve the scalability of neural network verification. We present a general description of the partitioning algorithm, implemented within the Marabou framework, and discuss its parameters and heuristic choices. In particular, we explore two novel partitioning strategies, that partition the input space or the phases of the neuron activations, respectively. We introduce a branching heuristic and a direction heuristic that are based on the notion of polarity. We also introduce a highly parallel pre-processing algorithm for simplifying neural network verification problems. An extensive experimental evaluation shows the benefit of these techniques on both existing and new benchmarks. A preliminary experiment with ultra-scaling our algorithm using a large distributed cloud-based platform also shows promising results.

17:30
Formal Methods with a Touch of Magic

ABSTRACT. Machine learning and formal methods have complimentary benefits and drawbacks. In this work, we address the controller-design problem with a combination of techniques from both fields. The use of black-box neural networks in deep reinforcement learning (deep RL) poses a challenge for such a combination. Instead of reasoning formally about the output of deep RL, which we call the {\em wizard}, we extract from it a decision-tree based model, which we refer to as the {\em magic book}. Using the extracted model as an intermediary, we are able to handle problems that are infeasible for either deep RL or formal methods by themselves. First, we suggest, for the first time, combining a magic book in a synthesis procedure. We synthesize a stand-alone correct-by-design controller that enjoys the favorable performance of RL. Second, we incorporate a magic book in a bounded model checking (BMC) procedure. BMC allows us to find numerous traces of the plant under the control of the wizard, which a user can use to better understand the wizard's operation and direct further training.

17:45
ART: Abstraction Refinement-Guided Training for Provably Correct Neural Networks

ABSTRACT. Artificial Neural Networks (ANNs) have demonstrated remarkable utility in various challenging machine learning applications. While formally verified properties of their behaviors are highly desired, they have proven notoriously difficult to derive and enforce. Existing approaches typically formulate this problem as a post facto analysis process. In this paper, we present a novel learning framework that ensures such formal guarantees are enforced by construction. Our technique enables training provably correct networks with respect to a broad class of safety properties, a capability that goes well-beyond existing approaches, without compromising much accuracy. Our key insight is that we can integrate an optimization-based abstraction refinement loop into the learning process and operate over dynamically constructed partitions of the input space that considers accuracy and safety objectives synergistically. The refinement procedure iteratively splits the input space from which training data is drawn, guided by the efficacy with which such partitions enable safety verification. We have implemented our approach in a tool (ART ) and applied it to enforce general safety properties on unmanned aviator collision avoidance system ACAS Xu dataset and the Collision Detection dataset. Importantly, we empirically demonstrate that realizing safety does not come at the price of much accuracy. Our methodology demonstrates that an abstraction refinement methodology provides a meaningful pathway for building both accurate and correct machine learning networks.

18:00-18:55 Session 9: Applied Verification
18:00
Automating Modular Verification of Secure Information Flow

ABSTRACT. Verifying secure information flow by reducing it to safety verification is a popular approach, based on constructing product programs or self-compositions of given programs. However, most such existing efforts are non-modular, i.e., they do not infer relational specifications for procedures in interprocedural programs. Such relational specifications can help to verify security properties in a modular fashion, e.g., for verifying clients of library APIs. They also provide security contracts at procedure boundaries to aid code understanding and maintenance. There has been recent interest in constructing modular product programs, but where users are required to provide procedure summaries and related annotations. In this work, we propose to automatically infer relational specifications for procedures in modular product programs. Our approach uses syntax-guided synthesis techniques and grammar templates that target verification of secure information flow properties. This enables automation of modular verification for such properties, thereby reducing the annotation burden. We have implemented our techniques on top of a solver for constrained Horn clauses (CHC). Our evaluation demonstrates that our tool is capable of inferring adequate relational specifications for procedures without requiring annotations. Furthermore, it outperforms an existing state-of-the-art hyperproperty verifier and a modular CHC-based verifier on benchmarks that involve loops or recursion.

18:15
Angelic Checking within Static Driver Verifier: Towards high-precision defects without (modeling) cost

ABSTRACT. Microsoft's Static Driver Verifier (SDV) pioneered the use of software model checking for ensuring that device drivers correctly use operating system (OS) APIs. However, the verification methodology has been difficult to extend in order to support either $(a)$ new classes of drivers for which SDV doesn't already have a harness and stubs, or $(b)$ memory-corruption properties. Any attempt to apply SDV out-of-the-box results in either \textit{false alarms} due to the lack of environment modeling, or \textit{scalability issues} when finding deeply nested bugs in the presence of a very large number of memory accesses.

In this paper, we describe our experience designing and shipping a new class of checks known as {\it angelic checks} through SDV with the aid of {\it angelic verification} (AV) \cite{das-cav15} technology, over a period of 4 years. AV pairs a precise inter-procedural assertion checker with automatic inference of {\it likely specifications} for the environment. AV helps compensate for the lack of environment modeling and regains scalability by making it possible to find deeply nested bugs, even for complex memory-corruption properties. These new rules have together found over a hundred confirmed defects during internal deployment at Microsoft, including several previously unknown high-impact potential security vulnerabilities. AV considerably increases the reach of SDV, both in terms of drivers as well as rules that it can support effectively.

18:30
Model Checking Software-Defined Networks with Flow Entries that Time Out

ABSTRACT. Software-defined networking (SDN) enables advanced operation and management of network deployments through (virtually) centralised, programmable controllers, which deploy network functionality by installing rules in the flow tables of network switches. Although this is a powerful abstraction, buggy controller functionality could lead to severe service disruption and security loopholes, motivating the need for (semi-)automated tools to find, or even verify absence of, bugs. Model checking SDNs has been proposed in the literature, but none of the existing approaches can support dynamic network deployments, where flow entries expire due to timeouts. This is necessary for automatically refreshing (and eliminating stale) state in the network (termed as soft-state in the network protocol design nomenclature), which is important for scaling up applications or recovering from failures. In this paper, we extend our model (MoCS) to deal with timeouts of flow table entries, thus supporting soft state in the network. Optimisations are proposed that are tailored to this extension. We evaluate the performance of the proposed model in UPPAAL using a load balancer and firewall in network topologies of varying size.

18:40
Using model checking tools to triage the severity of security bugs in the Xen hypervisor

ABSTRACT. In practice, few security bugs found in source code are urgent, but quickly identifying which ones are is hard. We describe the application of bounded model checking to triaging reported issues quickly at the cloud service provider Amazon Web Services (AWS). We focus on the job of reactive security experts who need to determine the severity of bugs found in the Xen hypervisor. We show that, using our publicly available extensions to the model checker CBMC, a security expert can obtain traces to construct security tests and estimate the severity of the reported finding within 15 minutes. We believe that the changes made to the model checker, as well as the methodology for using tools in this scenario, will generalise to other organisations and environments.

18:55-19:05Coffee Break
19:05-20:00 Session 10: Invited Talk II: Orna Kupferman
19:05
From Correctness to High Quality

ABSTRACT. In the synthesis problem, we are given a specification \psi  over input and output signals, and we synthesize a system that realizes \psi : with every sequence of input signals, the system associates a sequence of output signals so that the generated computation satisfies \psi . The above classical formulation of the problem is Boolean. The talk surveys recent efforts to automatically synthesize reactive systems that are not only correct, but also of high quality. Indeed, designers would be willing to give up manual designonly after being convinced that the automatic procedure that replaces it generates systems of comparable quality.

We distinguish between behavioral quality, which refers to the way the specification is satisfied, and costs, which refer to resources that the system consumes. For the first, we focus on the temporal logics LTL[F] and LTL[D], which extend LTL by quality operators [1]. The satisfaction value of LTL[F] and LTL[D] formulas is a real value in [0; 1], where the higher the value is, the higher is the quality in which the computation satisfies the specification. Essentially, LTL[F] contains propositional quality operators, like weighted-average, and LTL[D] contains discounted eventuality operators. Using LTL[F] and LTL[D], a designer can prioritize different ways to satisfy the specification and formally weight parameters such as security, maintainability, runtime, delays, and more. For the second, we distinguish between four classes of costs, induced by the following two characteristics: (1) construction vs. activity costs, and (2) physical vs. monetary costs. For example, the sensing cost of a system is physical, and we distinguish between the number of sensors in the system (construction cost) and the sensing required during its operation (activity cost) [2],[3].