ABSTRACT. This paper explores how artificial intelligence, and computational methods like ML can transform green hydrogen while overviewing green hydrogen production technologies. AI has already revolutionized manufacturing industries by turning complex data into useful insights. Now, it offers similar potential for hydrogen technology. This work shows various AI techniques used in green hydrogen production, including optimization strategies, predictive maintenance systems, and intelligent control systems. The review highlights AI-driven digital twins and hybrid architectures in electrolysis systems as particularly promising developments. Machine learning applications demonstrate significant improvements in production efficiency and cost reduction. This study emphasizes key challenges including data quality, standardization, and regulatory frameworks, while identifying future research directions in this fast-evolving field for cost-effective, and sustainable hydrogen production.

ABSTRACT. Content Addressable Memory (CAM) technology is transforming high-performance distributed network systems. It enables parallel searches across distributed infrastructures for instant packet routing and security decisions. CAM processes millions of packets per second with sub-microsecond latency, making it essential for large-scale distributed deployments. This paper examines CAM's role in distributed networking paradigms including Software-Defined Networking (SDN), Network Function Virtualization (NFV), and distributed data center architectures. CAM's parallel processing capabilities significantly enhance performance across distributed network nodes, improving packet classification, forwarding mechanisms, and security implementations. This work demonstrates CAM's impact on distributed network system scalability and consistent high-performance operations. However, challenges remain in power efficiency and cross-node coordination. The study highlights emerging trends including AI/ML integration, and edge computing applications. CAM continues evolving as a fundamental solution for high-performance distributed network infrastructures.

ABSTRACT. Scalar multiplication kP is the most frequently attacked operation in Elliptic Curve Cryptosystems (ECC). The atomicity principle and different atomic block patterns have been proposed in the past as effective means to counter simple Side- Channel Analysis (SCA) attacks. In this work, using our software and hardware implementations as an example, we show that the binary left-to-right kP algorithm with Chevallier-Mames atomic block patterns for point doubling and point addition is vulnerable to simple data-bit SCA attacks. Atomic blocks involving multiplications with special values like 1 are visibly distinguishable. For the right-to-left kP algorithm, this distinguishability is observable only in atomic patterns executed immediately after initialisation. We also show that the well-known randomisation of EC point coordinates, originally designed as a countermeasure against vertical attacks, is also effective against such data-bit SCA attacks.

ABSTRACT. The paper introduces a gain control enhancement applicable to both Continuous-Time Linear Equalizer (CTLE) and Variable Gain Amplifier (VGA) architectures, with implementation and analysis focused on the VGA topology. The proposed method introduces a set of NMOS transistors connected in parallel with the load inductors at the differential output nodes, enabling dynamic modulation of the effective inductive impedance. This configuration allows programmable shaping of the high-frequency response, particularly the resonant peak gain while maintaining stability across the low and mid-band frequencies. Unlike conventional gain control techniques, which often rely on resistive loading or tail current modulation and are associated with bandwidth degradation or linearity issues, the proposed approach leverages output stage impedance tuning. While the addition of parallel resistive paths inherently reduces the inductor’s quality factor and peak gain due to increased damping and power dissipation, the selective activation of NMOS devices provides a controllable trade-off between gain and bandwidth. A 2-bit thermometric control scheme is employed to ensure monotonic and predictable gain steps, with transistor sizing optimized to minimize parasitic capacitance and preserve resonant behavior. This architecture offers a compact and scalable solution for high-speed analog front-end designs, particularly in applications requiring fine-grained frequency response control without compromising area efficiency or signal integrity.

ABSTRACT. This paper presents a comprehensive comparative study of the deployment and performance of machine learning-based visual localization systems across various hardware platforms: CPU, GPU, NVIDIA Jetson, and FPGA. Using a dual-modality (RGB-IR) object detection framework based on the YOLO architecture, each platform’s suitability is assesed for real-time inference in terms of latency, throughput, power consumption, model complexity, and ease of deployment. The analysis highlights practical implications of deploying AI systems on edge and embedded platforms, with an emphasis on optimizing resource-constrained applications. The findings offer clear recommendations for selecting hardware platforms tailored to specific operational requirements. Furthermore, underscores the importance of hardware-aware model design, quantization, and efficient memory usage in enabling scalable and deployable visual intelligence. The work contributes in deploying deep learning models in production environments by offering practical, hardware-specific deployment insights and performance trade-offs. Keywords - Visual localization, hardware benchmarking, FPGA acceleration, YOLO, edge computing, real-time systems, CPU vs GPU performance, embedded AI, quantization.

ABSTRACT. Accurate circuit simulation is essential in electronic design automation (EDA), yet it is often constrained by the computational cost of complex device models. Detailed physical models improve simulation accuracy but lead to significant increases in simulation time, whereas simplified models can accelerate simulation at the expense of reduced accuracy. This paper presents an adaptive device model selection framework driven by machine learning, which predicts and assigns the most suitable model for each transistor instance based on extracted features. The framework performs pre-simulation analysis to automatically update the initially specified SPICE netlist, assigning the most appropriate device model to each instance based on circuit context, while maintaining a user-defined accuracy loss threshold. The proposed approach is evaluated on synthetically generated circuits with different model types. Experimental results demonstrate reductions in simulation runtime compared to reference simulations using complex device models, with accuracy loss maintained below an acceptable threshold of 10% by default. The method is fully compatible with standard EDA flows, providing enhanced simulation efficiency without necessitating manual customization.

ABSTRACT. The rapid advancement of integrated circuits has been driven by transistor miniaturization, high performance, and cost efficiency, yet these trends have also intensified reliability concerns. As supply voltage scaling lags for device scaling, circuits face adverse stress conditions that accelerate transistor degradation. Aging mechanisms such as bias temperature instability (BTI), hot-carrier injection (HCI), gate-oxide breakdown (GOX), and local transistor heating (LTE) progressively impact threshold voltage and drain current, thereby limiting the long-term lifetime of the circuit. These effects are also relevant for fundamental logic gates such as AND, NOR, and NOT, which in certain applications operate under overstress supply and signal voltages that exceed the safe long-term limits of the transistors in a given technology. In this work, we address the problem of overvoltage—one of the primary drivers of aging—by proposing a minimization method targeting aging-induced degradation in fundamental logic gates operating at supply levels exceeding the transistor stress tolerance of the given technology, with reliability evaluation based on transition time under aging conditions.

ABSTRACT. The thermal performance of power electronic systems is critically influenced by the ability to maintain uniform temperatures across semiconductor devices. In serially mounted semiconductor arrangements, forced-air cooling often produces a progressive heating effect, causing downstream devices to operate at higher temperatures. This non-uniform thermal loading leads to localised hotspots, accelerated material degradation, and reduced operational reliability. This paper investigates passive geometric optimisation of an air-cooled aluminium heatsink to enhance thermal uniformity across three serially mounted IGBTs. A computational numerical model was developed in ANSYS Fluent, using steady-state simulations and validated by experimental temperature measurements from a physical test rig. The baseline model demonstrated temperature differences across the length of the heatsink of up to 7.85°C at 100W, confirming the presence of a significant temperature gradient. Geometric modifications were evaluated in the form of a step- cut recess in the heatsink fins. The optimised geometry, with recess depths of 31 mm and 14 mm, reduced the temperature difference to 0.43°C under identical operating conditions, representing over 90% improvement compared to the unmodified design. The findings demonstrate that position- specific geometric tailoring of heatsinks offers a cost-effective and manufacturable solution to improve temperature synchronisation in multi-device power systems.

ABSTRACT. Processor testing is essential across all applications, particularly in safety-critical systems. In such systems, in-field testing plays a crucial role. Several testing methodologies have been developed, including offline testing, software-based testing, and online testing. While offline and software-based approaches face various limitations, online testing addresses some of these challenges but still suffers from limited fault coverage and requires complex pre-analysis. Moreover, none of these methods fully satisfies the requirements of in-field testing. This paper proposes Segmented BIST, an enhancement of online testing in which test execution is divided into smaller segments interleaved with the normal execution of the program. This technique is en- abled by introducing specific test instructions into the processor’s instruction set. Segmented BIST achieves efficient testing while increasing processor availability and enabling seamless program resumption and in-field testing. Furthermore, the proposed ap- proach provides an opportunity to incorporate a reseeding mech- anism that enhances fault coverage by dynamically modifying the test pattern generation. Experimental results demonstrate an increase in processor availability and a 4% improvement in fault coverage compared to conventional methods.

ABSTRACT. The paper is devoted to enumerating noise-resistant compositions of constant-weight codes with small values of the number of digits in codewords. The principles for identifying such compositions of constant-weight codes are established. Some of their characteristics of error detection in codewords are determined. In addition, special compositions of constant-weight codes are distinguished, the codewords of which are divided into pairs orthogonal in all bits. The use of such codes is effective in the synthesis of self-checking and controllable discrete devices according to two diagnostic features: belonging to the codewords of a given composition and belonging of the functions calculated in the concurrent error-detection circuits to the class of self-dual Boolean functions. The paper identifies two compositions with four bits in codewords that have this property. Compact structures of their self-checking checkers are given, and test vectors for them are indicated. The results obtained in the research of the authors of this paper can be effectively used in the construction of digital devices and systems for the detection of faults and errors in calculations.

ABSTRACT. This paper examines the behaviour of Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) using a model that is designed in MATLAB with a base paper reference from TSMC. The framework describes magnetization dynamics on the basis of the Landau-Lifshitz-Gilbert (LLG) equation and controls the switching properties through Monte Carlo simulations, including thermal noise. The findings reveal consistent coherent precessional switching whereby the value of $m_z$ is changed between $-1$ to $+1$ in 40--50~ns, which is just consistent with the experiments. Switching probability also changes abruptly between 0-100 percent in the current density of $1\times10^6$--$5\times10^6$~A/cm$^2$, which confirms practical device operation. Energy--delay analysis shows switching energy between 100--500~fJ and delay between 20--40~ns which similar results are reported in the literature. The equipment is stable to thermal (250--400~K) and damping (0.005--0.03) changes and performance measures have a variation less than 10 percent. Endurance Endurance is more than $10^6$ write cycles, and bit-error rates less than $10^{-9}$, and magnetic immunity is 3000~Oe. System- level testing ensures stable operation and zero failures during Monte Carlo testing as well as write operations were more powered and took longer than read. Altogether, this framework offers an effective and tested study instrument to analyze and optimize and comprehend the performance features of STT-MRAM.

ABSTRACT. DRAM and Flash memory controllers have gained a lot of popularity in recent years. They are widely used in applications ranging from smart phones to high performance computers. These applications require a large amount of memory access and higher bandwidth. Moreover, emerging AI applications are demanding more memory bandwidth for training and inference. However, memory-wall is still a bottleneck as data movement is a power hungry task and memory access has a long latency while memory bandwidth is limited. Further, these applications require large amount of memory storage. In this paper, we introduce the most recent techniques used to enhance DRAM and Flash memory controllers in terms of power, capacity, latency, bandwidth, and area.