ABSTRACT. In this work we discuss the vulnerability of atomic pattern algorithms for elliptic curve point multiplication against simple side-channel analysis attacks using our own implementation as an example. One of the assumptions, on which the atomicity principle is based, is the indistinguishability of operations with different registers, i.e. storing of the data into two different registers cannot be distinguished if their old and new data values are the same. But before the data can be stored in a register/block, this register/block has to be addressed for storing the data. Different registers/blocks have different addresses. The key-dependent addressing of registers/blocks is an inherent feature of the binary kP algorithms and allows to reveal the key k. In our work we demonstrated it. This means that the main assumption, that addressing of different registers/blocks is an indistinguishable operation, may no longer be applied when realizing kP implementations, at least not for hardware implementations.

ABSTRACT. Efficient data transfer and signal integrity are crucial in modern electronic systems and minimizing skew is a key aspect in achieving these objectives. As system frequencies continue to rise and signal integrity becomes more critical, the issue of temporal misalignment between signals poses significant challenges. The top-level design phase plays a crucial role in mitigating skew-related issues by carefully considering its impact on system performance. This paper focuses on the consideration of IO cells placement for skew minimization purposes during the top-level design implementation. It explores strategy and technique to optimize IO cell placement, ultimately reducing skew and enhancing system performance. Through practical examples, this paper provides valuable information for designers aiming to mitigate skew effects in their electronic system designs during top level design implementation.

ABSTRACT. Unintentional signal coupling between adjacent wires known as crosstalk is a common problem in integrated circuits (IC) and became major with operating frequencies rise and circuit dimensions decrease. Performance decline, signal distortion, and functional failures could all result from this phenomenon. Hence, having reliable crosstalk prediction and reduction mechanisms is a crucial aspect of IC design. Machine learning (ML) is currently a widely utilized technique in prediction algorithms. The suggested approach combines crosstalk analysis and ML to explore ways to predict crosstalk and reduce disturbances in ICs taking as input the physical design of IC. Training data for the ML model is collected from the parsing algorithm of IC information. Experiments are done for different types of designs (standard cells, memories, etc.). As a result, the trained ML model provides approximately 90% pass rate.

ABSTRACT. Scaling of process technology and the reduction of supply voltage are considered significant challenges for addressing IR drop and electromigration phenomena within the power supply network of integrated circuit. Conversely, disruptions in the power supply network contribute to the prevalent occurrence of aging mechanisms in sophisticated designs. Hence, having a reliable power supply network is a crucial aspect in the physical design of modern integrated circuits. Currently machine learning is a common method which is used in prediction algorithms, hence proposed algorithm uses machine learning for the prediction of power supply network architecture which will give more reliable power mesh for integrated circuits based on many physical design parameters, which are considered inputs for the proposed algorithm. The training data for the machine learning support is gathered from different power supply network architectures and designs with varying process sizes, gate counts, block sizes, floor plans, DCAP cell counts, and more. Experiments are also conducted for different Process, Voltage, and Temperature (PVT) conditions. Based on the collected data, distinct decision trees are created for predicting the appropriate power supply network architecture. The results indicate that the algorithm exhibits an approximate 13.57% inaccuracy rate using the currently implemented training data.

ABSTRACT. Abstract – Convolutional Neural Networks (CNNs) have achieved great success in various computer vision tasks. However, the computational demands of CNNs pose significant challenges in achieving real-time performance, especially when deploying them on resource-constrained devices. To accelerate visual odometry CNNs through the design and FPGA implementation for efficient hardware acceleration a new approach is proposed. A comprehensive methodology is presented that involves optimizing the CNN model architecture for Field-Programmable Gate Array (FPGA) deployment, designing custom hardware modules tailored for CNN computations, and leveraging parallelism to exploit the inherent parallel processing capabilities of FPGAs. The approach demonstrates significant speedup compared to traditional software implementations, achieving real-time performance for demanding computer vision tasks. Experimental results showcase the effectiveness of the design, highlighting the potential of Field-Programmable Gate Array (FPGA) based acceleration for CNN models. This work provides valuable insights into the design and implementation of CNNs on FPGAs, paving the way for the efficient deployment of deep learning models in resource-constrained environments.

ABSTRACT. In AMS circuits, the defect simulation time is increasing prohibitively as the circuits are becoming more and more complex. In addition to this, as the need for high defect coverage is increasing due to standards such as ISO26262, the defect simulation time is further increasing. In this paper, we present an ultra-fast defect simulation framework to test defects in pre-silicon testing of AMS circuits. We Achieve time efficiency by means of two methods: (1) Improving the defect injection mechanism and (2) Circuit partition. To realize a given defect model, we use Verilog-A modules using which we can inject nearly all the defects in a circuit with a single test run (for a given test condition) which reduces the average defect simulation time. In addition to this, we also incorporate partitioning of the circuit under test into sub circuits using graph theory. The main idea here is that testing individual strongly connected components (SCCs) separately is comparatively more time-efficient rather than testing the entire circuit together. For robust framework validation, we utilize a benchmark circuit containing common analog circuits like operational amplifiers, bandgap references, Widlar current references, and bias generation circuits designed in UMC65nm technology. For the defect detection, we consider the voltage values at strategically chosen voltage nodes in the circuit and compare them with the values expected from a defect-free circuit. Using extensive simulations, we show that using our method, the defect simulation time can be improved by 17X in comparison with conventional methods. Additionally, the proposed method is independent of defect model or detection method.

ABSTRACT. The demand for reliable and defect-free electronics is growing steadily, driven by the requirements of mission-critical industries like automotive, space, and medical sectors. While there have been substantial advancements and extensive research focused on defect detection in digital circuits over the past four decades, the importance of defect detection in analog circuits has gained prominence more recently, primarily due to the increased utilization of electronic components in the automotive industry. This work aims to provide a concise review of several defect detection techniques for various analog and mixed-signal (AMS) circuits, employing digital control and monitoring circuits. This review aimed to encompass various analog and mixed-signal (AMS) circuits, including operational amplifiers (Op Amps), Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs), conventional LDOs (low-dropout regulators), fast transient flipped voltage follower (FVF) LDOs and Phase Locked Loops (PLL). By employing digital control and monitor circuits, the discussed methods harness the strengths of digital circuits, such as precise control, ease of analysis, and efficient testing. This utilization of digital circuitry in defect detection for analog circuits allows for improved accuracy, enhanced reliability, and simplified implementation.

ABSTRACT. The silicon bandgap voltage at zero kelvin, VGO, is a physical constant independent of the process, supply voltage and temperature. Hence extracting this voltage accurately would help in designing precision voltage or current reference circuits. In this paper, we present a holistic strategy to design a high-precision voltage reference circuit by extracting the silicon bandgap voltage which, theoretically, can have ultra-low temperature coefficient (TC) of <1ppm/C. The proposed method is validated in theory as well as with transistor-level design simulations. Furthermore, we confirm the proposed method with measurement results using a system designed with diode connected BJTs fabricated in UMC 65nm process technology and active circuitry realized using discrete components. The best TC of 3.4ppm/C over 125C temperature range is achieved in silicon. We also discuss the main sources of errors that would affect the performance of the proposed bandgap reference along with the best practices to mitigate these errors.