ABSTRACT. Prof. Nunez-Yanez is a professor in hardware architectures for Machine Learning at Linköping University, Sweden since 2022 within the WASP program in autonomous systems. He holds a PhD in hardware-based parallel data compression from the University of Loughborough, UK. Previously to joining Linköping University he was a reader (associate professor) at Bristol University, UK. He spent several years working in industry at ST Micro (Milan, Italy), ARM (Cambridge, UK) and Sensata Systems (Swindon, UK) with Marie Curie and Royal Society fellowships. His main area of expertise is in the design of hardware architectures and heterogeneous systems for signal processing and machine learning with a focus on run-time adaptation, high-performance via parallelism and energy-efficiency.

ABSTRACT. Low Density Parity Check (LDPC) codes under iterative decoding have shown remarkable error correction capabilities, with moderate complexity requirements. Initially, in this paper a check based on a part of the parity check matrix (core part check) is presented. The proposed check is amenable for hardware implementation and allows the termination of the decoding procedure at a sub-iteration level, i.e., within an iteration. In this way the number of clock cycles required reduced by 150 for the semi-parallel architecture and for 5G NR codes. Simultaneously the Block Error Rate (BLER) remains the same while hardware becomes simpler. In addition, this paper introduces a novel scheduling scheme combined with the core part check and a syndrome-select logic. Experimental results are offered, assuming the parallel architecture, which show that the proposed rescheduling reduces the average number of required clock cycles per decoded word. Simultaneously improves the BLER utilizing exactly the same hardware. Specifically, targeting 5G NR LDPC codes, gains of 35\% are achieved, for both the OMS and NMS algorithms. Furthermore, an innovative approach for the merge network of the reconfigurable barrel shifter is proposed. Finally, an ASIC implementation for semi-parallel architecture and the energy consumption gained with the proposed algorithm are presented.

ABSTRACT. Wireless attacks targeting the Internet of Things (IoT) pose challenges to its security. To counter this threat, in-depth security mechanisms such as Intrusion Detection Systems (IDSs) are used. The implementation of IDSs in edge devices is challenging, considering the inherent constrained nature of IoT devices. In this paper, three Intrusion Detection System (IDS) implementation approaches, software, in-core hardware, and off-core hardware are defined and compared, using an IoT-context representative case study. Advantages and disadvantages of each approach are assessed and discussed, comparing design time, ease of maintenance, detection performance and SoC resource utilization. Our results, relative to the SoC baseline, show that the software approach used 17.92% more energy consumption per packet(+0.19mJ/p) than the hardware approach. Conversely, the hardware approach results in a significant overhead of FPGA resources, requiring up to 12.06% more LUT and 7.75% more FF.

ABSTRACT. Efficient memory management is essential for signal and image processing systems, particularly in data-intensive applications where performance and resource constraints are critical. This paper presents a comparative study of two advanced memory optimization techniques: Memory Script Optimization (MSO), and Passive Active Flow Graph (PAFG) Optimization—within the context of dataflow-modeled applications. Both approaches aim to reduce memory usage and improve execution efficiency, but they do so with distinct strategies: Memory Scripts focus on in-place buffer management, while PAFG modifies actor interactions to minimize buffer requirements. Using a portion of a Convolutional neural network (CNN) application as a case study, we evaluate the efficiency of these techniques in terms of memory reduction and execution time. Our results demonstrate that MSO provides significant performance improvements, achieving up to 17% memory savings and 21% faster execution times, making it ideal for independent data operations. However, PAFG offers greater scalability and flexibility, particularly when dealing with complex data dependencies, and provides a simpler path to implementation. This work not only highlights the tradeoffs between memory efficiency and flexibility but also paves the way for applying these optimizations in near-memory computing architectures, where distance from memory to processing is employed as a parameter to improve efficiency.