CFP

DVCon Taiwan 2023: DVCon Taiwan

NYCU

Hsinchu, Taiwan, September 7, 2023

Conference website	http://dvcontaiwan.org
Submission link	https://easychair.org/conferences/?conf=dvcontaiwan2023
Abstract registration deadline	May 15, 2023
Submission deadline	August 7, 2023

Topics: verification and validation design automation

The Design & Verification Conference (DVCon) is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated circuits.

This highly technical conference focuses on the practical aspects of design and verification techniques and the use of standards in leading-edge projects, with the goal of facilitating the improvement and maturation of design and verification techniques throughout the industry by encouraging attendees to adopt and reference similar techniques in their own development flow.

Submission Guidelines

The DVCon Taiwan Steering Committee invites submissions of papers and presentations on practical experiences and novel applications of standards in various areas. Submissions on topics in the following areas are encouraged, but not limited to:

■ Verification and Validation

Advanced methodologies and test-benches
Verification processes, regressions and resource management
Debug and analysis of complex designs
Multi-language design and verification
Hardware/Software co-design and co-verification of embedded systems

■ Design and Verification Reuse / Automation

Bridging verification and validation across multiple engines SoC and IP integration methods and tools
Applications of the Accellera Portable Stimulus Standard
Configuration management of IP and abstraction levels
Interoperability of models and/or tools
High-level synthesis from ESL languages
Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping

■ Machine Learning and Big Data

Automating the Optimization of Verification / Implementation Processes
Coverage metrics and data analysis
Performance modeling and/or analysis

■ Low-Power Design and Verification

Low-power design and verification
Clock domain crossing verification
Power modeling, estimation and management

■ Safety-Critical / Security-Critical Design and Verification

Verification and DO-254 compliance
Automotive ISO 26262 Design and Verification Challenges
Medical or Industrial Verification Challenges
Requirements-Driven Verification Methodologies
IP protection and security

■ Mixed-Signal Design and Verification

Mixed-signal design & verification techniques
Real-value modeling approaches
Application of mixed-signal extensions for UVM

DVCon Taiwan has adopted the following process to reduce the amount of time and effort required to prepare for the submission of papers.

We accept submissions in the form of a paper (short paper, 2-6 pages) or slides (6 pages slides plus 100-words abstract)
Both formats are available in English and Mandarin
Submitted papers and slides will be reviewed by the Technical Program Committee under the DVCon Taiwan Steering Committee and will be considered for presentation at DVCon Taiwan
Presentation time at the conference will be 30 minutes, including Q&A
As with other regional DVCons, corporate logos may only be included on the title slide of the presentation
Please use the templates provided for both papers and slides

https://dvcontaiwan.org/author/

Committees

Program Committee

Yung Jen Chen, Realtek
SJ Wu, Anshingtek

Organizing committee

Penny Yang, Synopsys
Ying-Cherng Lan, Cadence
Michael Chiang, Siemens
Alan Su, eNeural
Jim Kung, MediaTek
Leo Chen, Micron
Prosper Chen, AMD

Venue

NYCU, Hsinchu, Taiwan (新竹陽明交通大學光復校區電資大樓)

https://eic.nycu.edu.tw/

Contact

All questions about submissions please email to dvcon.tw@gmail.com