CFP
WRTLT 2018: Workshop on RTL and High Level Testing 2018 Hefei, China, October 18-19, 2018 |
Conference website | http://wrtlt2018.hfut.edu.cn |
Submission link | https://easychair.org/conferences/?conf=wrtlt2018 |
Submission deadline | September 27, 2018 |
Topics: rtl fault modeling/atpg/dft/bist high level/behavior fault modeling 3d ic testing soc/noc testing
The goal of this workshop is to bring researchers and practitioners of VLSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL) and high level testing. WRTLT'18, the 19th workshop, will be held in conjunction with the 27th Asian Test Symposium (ATS'18) in Hefei, Anhui.
Submission Guidelines
All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome:
- Analog/Mixed-Signal Test
- RTL fault modeling, RTL ATPG, RTL DFT, RTL BIST
- High-level/behavior fault modeling, testing and synthesis for testability
- Functional fault modeling and test bench generation
- 3D IC testing
- SoC/NoC testing, test scheduling, core-based testing, interconnect testing
- Dependable SoC: design for dependability, self-repair techniques, fault-tolerant SoCs
- Microprocessor testing and design verification
- Low power testing and Test compression
- Hardware trojan detection and secure testing
Committees
Program Committee
- Huaguo Liang
- Maoxiang Yi
- Xiaowei Li
- Jia Jing
Organizing committee
- Xiaowei Li
- Aibin Yan
- Zhengfeng Huang
- Haochen Qi
Contact
All questions about submissions should be emailed to huangzhengfeng@139.com