Workshop on Artificial Intelligence and Computer Architecture (WAICA)

Co-located with the 16th HiPEAC Conference on High Performance and Embedded Architectures and Compilation 

Artificial intelligence (AI) is increasingly transforming industries, services, jobs and even whole societies. Thanks to powerful algorithms, today's information systems are able to solve complex problems in areas as varied as structural engineering, medicine, genetics, environment and transportation, while machine learning is even improving how computers themselves are developed. Meanwhile, new hardware developments, such as heterogeneous architectures which deliver energy savings without compromising performance gains, offer AI exciting opportunities for development. Linking both software and hardware, from embedded systems to high-performance computing (HPC) platforms, can inspire creative solutions which can improve both individuals' quality of life and society as a whole.

This two-part workshop will delve into this fascinating and influential field from both the technology and application sides. The first part will feature presentations on how novel computer architectures are powering artificial intelligence applications, or conversely how artificial intelligence is helping develop innovative computer architectures.

In the second part, there will a discussion panel exploring what kind of applications AI is being used for in daily life, with a particular focus on applications related to HPC. The panel will also explore parallelism efforts and platforms suitable for AI in HPC.

Submission Guidelines

WAICA will not publish workshop proceedings. Papers should be 4 to 8 pages long, and submitted in PDF format. Authors are free to publish in other venues subsequently. Topics of interest include, but are not limited to:

• Domain-specific architectures for machine learning applications
• Self-learning/self-improving computing systems
  • AI-based solutions for computer architecture problems such as design/optimization of components in computer architecture and systems, such as branch predictor, cache, memory, I/O, interconnects, etc. performance/reliability/energy/security prediction
  • Compiler optimizations
• Architecture-aware code optimizations for machine learning applications
• Architecture-specific implementations of machine learning algorithms

Committees

Program Committee

• Sanem Arslan (Marmara University)
• Chris Fensch (ARM Trondheim)
• Xavier Martorell (Universitat Politècnica de Catalunya)
• Smail Niar (LAMIH/CNRS, Polytechnic University Hauts-de-France)
• Ozcan Ozturk (Bilkent University)
• Antonio Portero (Jülich Supercomputing Center)
• Gladys Utrera (Universitat Politècnica de Catalunya)
• Gulay Yalcin (Abdullah Gul University)
• Buse Yılmaz (Istinye University)

Organizing committee

• Raffaella Folgieri (University of Milan)
• Marisa Gil (Universitat Politècnica de Catalunya)
• Isil Oz (Izmir Institute of Technology)