SPL2023: XI Southern Programmable Logic Conference San Luis, Argentina, March 27-31, 2023 |
Conference website | http://www.splconf.org/spl23/ |
Submission link | https://easychair.org/conferences/?conf=spl23 |
Submission deadline | November 15, 2022 |
SPL is an international conference for researchers and developers interested in reconfigurable logic technology and its applications. The SPL2023 will take place in San Luis, Argentina. The XI edition continues the tradition of previous ones to become the meeting point for the worldwide community in the area.
Submission Guidelines
All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome:
- Authors are invited to submit original and unpublished contributions as 6-page full papers, which must be written in English. Best papers will be selected to be published in the IEEE Embedded Systems Letters, which provides excellent visibility and accessibility to its contents.
- Also, a Designer Forum is available, to give exposure to ongoing works, academic experiences and industrial designs, and get feedback from experienced researchers and industrial partners. Authors are invited to submit 4-page short papers, which can be written in English, Spanish or Portuguese. Accepted contributions will be included in a separate proceedings volume.
SPL uses a double-blind review system. Authors need to ensure that their manuscripts are prepared not to give away their identity. Besides to hide names and affiliations under the title, other considerations need to be taken. References to previous work should be made in third person, and if necessary to maintain anonymity, its could be shown as "Removed for blind review", but consider that this may impede a thorough review. Remove references to funding sources and acknowledgments. Make sure that figures and file's metadata do not contain any identifying information.
List of Topics
SPL covers a broad spectrum of topics related to programmable logic including, but not limited to:
- Design Methodology and Tools
- High Performance Computing, Acceleration, Data Processing
- Reconfigrable Logic and Adaptive Designs
- Architectures and Technologies
- Applications and Benchmarks
- High-Level Abstraction
- Hardware/software co-design
- Survey, Trends, Education
Organizing Committee
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General Chair
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Julio Dondo Gazzano - Universidad Nacional de San Luis (UNSL, Argentina)
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Program Co-Chairs
- Carlos Vaderrama Sakuyama - Université de Mons, Department of Electronics and Microelectronics (SEMI, Belgica)
- Fernando Rincon Calle - Universidad de Castilla-La Mancha (UCLM, España)
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Proceedings Co-Chairs
- Elias Todorovich - Universidad Nacional del Centro de la Provincia de Buenos Aires (UNICEN, Argentina)
- Juan Pablo Soto Barrera - Universidad de Sonora (UNISON, Mexico)
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Designer Forum Chair
- Cristian Sisterna - Universidad Nacional de San Juan (UNSJ, Argentina)
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Financial Co-Chairs
- Ricardo Cayssials - Universidad Tecnologica Nacional Bahia Blanca (UTN BHI, Argentina)
- Cristian Falco - Universidad Nacional de San Luis (UNSL, Argentina)
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International Relationship Chair
- Gustavo Suter - Universidad Autonoma de Madrid (UAM, Spain)
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Local Chair
- Carlos Federico Sosa Paez - Universidad Nacional de San Luis (UNSL, Argentina)
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Local Committee
- Diego Costa - Universidad Nacional de San Luis (UNSL, Argentina)
- Roberto Kiessling - Universidad Nacional de San Luis (UNSL, Argentina)
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Publicity Chairs
- Rodrigo Alejandro Melo - indie Semiconductor (Argentina)
- Astri Edith Andrada Tivani - Universidad Nacional de San Luis (UNSL, Argentina)
Workshops
Three days of intensive workshops will be organized to encourage hardware digital design skills on advance students and professionals. These workshops will be lectured by Xilinx, Microchip and Electratraining experts in the field of hardware design and programmable logic.
FPGA-based Accelerated Cloud Computing with AWS EC2 F1 and SDAccel
Tutorial Date: March 27, 2023
Presenters: Sergio Lopez-Buedo & Gustavo Sutter, Electratraining
Abstract: The evolution of reconfigurable computing in recent decades following Moore's law was impressive. Xilinx (now AMD) was the inventor of the FPGA back in the early 80s, later introduce Adaptable SoC (system on a chip) and recently the ACAP (Adaptive Computing Acceleration Platform) architecture. The evolution in terms of computing power is several orders of magnitude, leading to new tools and design methodologies, and also enabling new applications and uses of the technologies. This course reviews the key ideas in new devices and methodologies applied to embedded systems and cloud based HPC (High Performance Computing) platforms.
Developing Accelerators for AMD Xilinx adaptive computing platforms
Tutorial Date: March 28, 2023M
Presenter: Xilinx
Abstract: This tutorial will introduce the Vitis Unified Software Platform environment for developing FPGA accelerators. Vitis environment enables the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems. Vitis supports: C and C++ kernels. RTL design flows are also supported for experienced hardware developers. Each of these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source accelerated libraries. We will also introduce the PYNQ project and show how PYNQ makes the use of Xilinx accelerator much easier.
Invited Speakers
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SYNOPSYS: Title: Digital IC Design Flow – From the Idea to the Chip
Sponsors
AMD-XILINX
MICROCHIP
SYNOPSYS
Contact
All questions about submissions should be emailed to jdondo@unsl.edu.ar