REV-A 2018: Re-Emergence of Vector Architectures Workshop IEEE Cluster 2018 Belfast, Ireland, September 9, 2018 |
Conference website | https://rev-a.github.io/ |
Submission link | https://easychair.org/conferences/?conf=reva2018 |
Submission deadline | July 2, 2018 |
Notification of Acceptance | July 17, 2018 |
The commoditization of high performance computing to a broader range of applications coupled with the reduction in performance improvement from traditional scaling technologies has led to a broad interest in a number of new compute acceleration technologies from GPGPUs to CGRAs and FPGAs. Meanwhile, SIMD widths have been widening to try to keep up with computational demand and general purpose architectures have started incorporating features from the vector architectures that used to dominate high performance computing. From IBM's Vector Media eXtension (VMX) to NEC's SX architecture to Intel's Advanced Vector eXtension (AVX) to ARM's recently announced Scalable Vector Extension (SVE) -- all of the major general purpose architectures seem to have embraced a return to vector based functionality.
Supporting these hardware developments there are a number of features being proposed for incorporation into modern programming models and languages in order to support the vector additions as well as restructuring memory access in order to feed the computational pipelines. Meanwhile application developers have been hard at work trying to refactor code to take advantage of wider vector units and more complicated memory hierarchies. Tools and techniques for developing for these new vector architectures are still evolving, particularly on emerging languages and runtimes.
Submission Guidelines
cList of Topics
The REV-A 2018 workshop will be a full-day meeting to be held at the IEEE Cluster 2018, in Belfast, Ireland, focusing on all aspects of vector architectures, programming models, programing frameworks, and applications. Topics of interest, of both theoretical and practical significance, include but are not limited to the following topics:
- Programming framework
- Programming model and language explorations
- Compilation and optimization including:
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- algorithmic improvements
- code optimization
- Performance Analysis and Debugging Tools
- Performance Metrics and Evaluations
- Libraries and run-time systems
- Design, generation, verification and validation of representative applications
- Case-studies of representative applications
- Innovative applications for vector architectures
- Hardware studies and micro-architectural implementation tradeoffs
Committees
Program committee
Giri Chukkapalli | Cavium |
Elmootazbellah Elnozahy | KAUST |
Ali Jannesari | Iowa State University |
Ian Karlin | Lawrence Livermore National Laboratory |
Sanyam Mehta | Cray Inc. |
Jose Moreira | IBM |
Hiroshi Nakashima | Kyoto University |
Lawrence Rauchwerger | Texas A and M University |
Erven Rohou | INRIA |
Mitsuhisa Sato | RIKEN |
Albert Sidelnik | NVIDIA |
Xinmin Tian | Intel |
Mateo Valero | Barcelona Supercomputing Center / UPC |
Jeffrey S. Vetter | ORNL |
Pen-Chung Yew | University of Minnesota |
Organizing committee
- Luiz de Rose (Cray)
- Eric Van Hensbergen (Arm)
Venue
The conference will be held in conjunction with Cluster 2018 in Belfast, Ireland
Contact
All questions about submissions should be emailed to eric.vanhensbergen@arm.com