ITC India 2017: International Test Conference (India) 2017 Bangalore, India, July 10-12, 2017 |
Conference website | http://www.itctestweekindia.org |
Abstract registration deadline | April 30, 2017 |
Submission deadline | April 30, 2017 |
About ITC INDIA 2017
International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems—covering the complete cycle from design verification, design-for- test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement. At ITC, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. This ITC conference will be focusing on Test technology development in Asia and India but the submissions may not be limited to topics related to this region. Topics related to DFT and test development across multi geographical regions will be of special interest.
This conference is being held in India under the International Test conference banner to invite researchers, industry teams to present their development work which has a focus on ASIA. This includes design teams which have multiple national presences and are developing designs and products across multiple sites across the world.
Submission Guidelines
All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome:
- Full papers:
Authors are invited to submit original, unpublished papers describing recent work in the field of test and design. In addition, authors are invited to submit high quality, practical, industry best practices. Submissions simultaneously under review or accepted by another conference, symposium or journal, will be summarily rejected.
Submissions must include:- Title of paper.
- Name, affiliation, e-mail address of each author.
- The corresponding author(s). ITC will communicate with the corresponding author(s).
- One or two topic(s) from the topic list, or a description of your topic.
- An electronic copy of a complete paper up to 10 pages , or an extended summary up to 6 pages. Submissions less than 4 pages are rarely accepted.
- An abstract of 500 words or less to be entered online.
Paper submission deadline: Mar 31, 2017
Author notification: May 19, 2017
Final manuscript due: June 16, 2017
- Posters:
Authors are also invited to submit a single-page poster proposal. Posters are a useful way of presenting late-breaking results, getting feedback on an innovative method, or participating without having to write a full paper. Acceptance as a poster does not preclude submission of a more complete work as an ITC paper in 2017. Poster proposal abstracts should be no longer than a single page.
Poster submission deadline: April 21, 2017
Author notification: June 2, 2017
Final manuscript due: June 16, 2017
List of Topics
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3D/2.5D Test
Adaptive Test in Practice
ATE/Probe Card Design
Advances in Boundary Scan
Bring Up
Data Driven Methods
Data Exchange and Infrastructure
Defect-Oriented Testing
DFM and Test Diagnosis
Economics of Test
End-to-End Data Analysis
Embedded BIST & DFT
Emerging Defect Mechanisms
Hardware Security and Trust
IoT Testing
Jitter, High-Speed I/O and RF Test
Known-Good-Die testing
Memory Test and Repair
MEMS Testing
Mixed-Signal and Analog Test
New Technologies and Test
On-Chip Test Compression
Online Test
Pre- and Post- Silicon Validation
Power Issues in Test
Protocol-aware Test
Reliability and Resilience
Scan Based Test
SoC/SiP/NoC Test
Silicon Debug
Simulation and Test
System Test (Applications)
System Test (Hardware/Software)
Test-to-Design Feedback
Test Escape Analysis
Test Flow Optimizations
Test Generation and Validation
Test Resource Partitioning
Test Standards
Test Time Analysis and Reduction
Testing High Speed Optics/Photonics
Timing Test
Yield Analysis and Optimization
Committees
Advisory Committee
- Yervant Zorian, IEEE Fellow, TTTC President
- Rohit Kapoor, IEEE Fellow, TTTC 2nd Vice Chair
- Souvik Mahapatra, IEEE Fellow, IIT Mumbai
- Scott Davidson, TC USA Liaison
Steering Committee
- Prasad Mantri, Principal Engineer, Microelectronics Group, Oracle Systems Group
- Navin Bishnoi, Deputy Director, ASIC Product Development, GlobalFoundries
- Thryambak Chandilya, Applications Engineering Manager-DFT, Mentor Graphics
- Venkata Rangam Totakura, Design Engineering Director, Cypress Semicontor Tech.
- Nagesh Tamarapalli, Fellow, AMD India Design Center
- Jyotirmoy Saikia, Senior Staff R&D Engineer, Test R&D, Synopsys
- Anurag Gupta, Director Engineering, Mobile Soc Development, LG Soft India
- Manu Lakshmanan, Principal Application Engineer. Cadence Design System, India
- Prof Vijendra Singh, Professor, IIT Mumbai
- Keshav Bapat, General Manager, Keysight Technologies
Venue
The conference will be held in Bangalore, India during July 10-12, 2017.
Contact
All questions about submissions should be emailed to navin.bishnoi@globalfoundries.com