VLSI-SOC 2017: 25TH IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION
PROGRAM

Days: Monday, October 23rd Tuesday, October 24th Wednesday, October 25th

Monday, October 23rd

View this program: with abstractssession overviewtalk overview

09:30-10:30 Session 2: Morning Keynote
09:30
Robustness Challenges in the Internet of Things ( abstract )
11:00-12:30 Session 3A: Digital architectures: NoC, multi-core, and reconfigurable
11:00
Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets ( abstract )
11:30
Low-Overhead Asymmetric Frequency Control for On-Chip Network Interconnects ( abstract )
12:00
Power-aware and Cost-efficient State Encoding in Non-volatile memory based FPGAs ( abstract )
11:00-12:30 Session 3B: Embedded systems: Architecture, design, and software
Chair:
11:00
Intelligent Embedded and Real-Time ANN-based Motor Control for Multi-Rotor Unmanned Aircraft Systems ( abstract )
11:30
Extending OpenVX for Model-based Design of Embedded Vision Applications ( abstract )
12:00
Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors ( abstract )
13:45-14:45 Session 5: Poster Session
13:45
A Low power 6-bit FLASH ADC using Charge steering amplifier For RF Application ( abstract )
13:45
On the In-field Testing of Spare Modules in Automotive Microprocessors ( abstract )
13:45
Restoration protocol: Lightweight and secure devices authentication based on PUF ( abstract )
13:45
Implementation and Analysis of Hotspot Mitigation in Mesh NOCs by Cost-Effective Deflection Routing Technique ( abstract )
13:45
Non-Regression Approach for the Behavioral Model Generator in Mixed-Signal System Verification ( abstract )
13:45
A sub-µW Bio-potential Front End in 65nm CMOS ( abstract )
13:45
Applying IJTAG-Compatible Embedded Instruments for Lifetime Enhancement of Analog Front-Ends of Cyber-Physical Systems ( abstract )
15:00-16:30 Session 6A: Prototyping, verification, modeling, and simulation
15:00
A New Approach For Constructing Logic Functions After ECO ( abstract )
15:30
Exploring the Use of the Finite Element Method for Electromigration Analysis in Future Physical Design ( abstract )
16:00
Multiple Reset Domains Verification Using Assertion Based Verification ( abstract )
15:00-16:30 Session 6B: Hardware Security
15:00
Process-Aware Side Channel Monitoring for Embedded Control System Security ( abstract )
15:30
DFS Covert Channels on Multi-Core Platforms ( abstract )
16:00
Pushing the Limits Further: Sub-Atomic AES ( abstract )
Tuesday, October 24th

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10:30-12:00 Session 9A: Low-power and thermal-aware IC design
10:30
Prediction Horizon vs. Efficiency of Optimal Dynamic Thermal Control Policies in HPC Nodes ( abstract )
11:00
Early-Bird Sampling: a Short-Paths Free Error Detection-Correction Strategy for Data-Driven VOS ( abstract )
11:30
Level-shifter-less Approach for Multi-VDD Design to use Body Bias Control in FD-SOI ( abstract )
10:30-12:00 Session 9B: Analog, mixed-signal and sensor architectures I
10:30
Robust, Self-Timed Power on Reset Circuit for Low Voltage Applications ( abstract )
11:00
A 2×VDD-Enabled Fully-Integrated Low-Dropout Regulator with Fast Transient Response ( abstract )
11:30
Single charge-pump generating high positive and negative voltages driving common load ( abstract )
12:00-13:15 Session 10: Luncheon Keynote
12:00
Building World Class R&D Capacity in Semiconductor Technology ( abstract )
13:15-14:45 Session 11A: Special Session I: Physical Design and Mask Synthesis for Advanced Lithography Technology
13:15
Design Optimization for Directed Self-Assembly ( abstract )
13:37
Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review ( abstract )
14:22
Redundant Via Insertion in SADP Process with Cut Merging and Opitmization ( abstract )
15:07
Advanced Data Analytics and Machine Learning for VLSI Design-to-Process and Yield Optimization ( abstract )
Wednesday, October 25th

View this program: with abstractssession overviewtalk overview

09:00-10:00 Session 13: Morning Keynote
09:00
Design for Security: The Hardware-Up Principle ( abstract )
10:30-12:00 Session 14A: Analog, mixed-signal and sensor architectures II
10:30
A 86 nA and sub-1 V CMOS voltage reference without resistors and special devices ( abstract )
11:00
A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation ( abstract )
11:30
Σ-Δ Based Force-Feedback Capacitive Micro-machined Sensors: Extending the Input Signal Range ( abstract )
10:30-12:00 Session 14B: Variability, reliability, and test
10:30
Analyzing the Behavior of FinFET SRAMs with Resistive Defects ( abstract )
11:00
Library Pruning and Sigma Corner Libraries for Power Efficient Variation Tolerant Processor Pipelines ( abstract )
11:30
Improving post-silicon error detection with topological selection of trace signals ( abstract )
13:00-14:30 Session 15A: Emerging technologies and applications
13:00
Enabling Efficient System Design Using Vertical Nanowire Transistor Current Mode Logic ( abstract )
13:30
Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays ( abstract )
14:00
A Wearable Neuro-Degenerative Diseases Detection System based on Gait Dynamics ( abstract )
13:00-14:30 Session 15B: Circuits and systems for signal processing and communications
13:00
A Low Power, Programmable Bias Inverter Quantizer (BIQ) Flash ADC ( abstract )
13:30
Low-Jitter Plain Vanilla CMOS CDR with Half-Rate Linear PD and Half Rate Frequency Detector ( abstract )
14:00
A Pulsed-Data Technique for Single-channel, Dynamic Signaling for IoT Applications ( abstract )
15:00-16:30 Session 16A: CAD: Synthesis and analysis
15:00
Template based synthesis for high performance computing ( abstract )
15:30
Synthesis of Multi-variate Stochastic Computing Circuits ( abstract )
15:00-16:30 Session 16B: Special Session II: Emerging topics in security
15:00
Continuous Authentication of UAV Flight Command Data using Behaviometrics ( abstract )
15:30
A Multiple Valued Logic Approach for the Synthesis of Garbled Circuits ( abstract )
16:00
Evolution of Logic Locking ( abstract )