ABSTRACT. In many engineering areas complex systems are composed of sub-parts that are modeled and analyzed in very different ways. These subsystems are often heterogeneous parts of the complex system that have to be analysed or designed in a communal environment. This has been triggering the development of ``open'' numerical subsystems that can be ``glued'' together in a shared numerical ``backplane''. In the literature the full simulation of the complex heterogeneous system is referred to with several names and among these with co-simulation. In this paper we use MATLAB as a backplane and present an environment for the analysis of heterogeneous systems where the electrical sub-parts can be efficiently modeled and analysed.

ABSTRACT. Machine learning flooded many research fields, including Electronic Design Automation (EDA). The availability of algorithms that can solve complex problems through generic rule formulations represent a fresh opportunity to improve existing design paradigms. In this work we investigate the use of machine learning to manipulate logic circuits. More specifically, we envision the use of Classification and Regression Trees (CARTs) as tools for modeling generic Boolean functions through a representative subset of core expressions, what we call the activation kernels. Experiments conducted on a subset of opensource benchmarks demonstrate that CARTs are indeed able to identify the activation kernels that cover whole Boolean functions with a high degree of accuracy (89% on average). In order to quantify other figures of merit, we also provide a physical implementation of such activation kernels. Results show that the obtained circuits are amazingly smaller than standard-cell based circuits synthesized through a classical logic synthesis flow (16X less devices on average).

ABSTRACT. The Internet of Things (IoT) brings forth pressing requirements on the service providers in terms of service differentiation, which plays an important role in pricing policies as well as network load balancing. In this paper, we consider differentiation of application level protocols for IoT from general application protocols through flow classification. We implement a neural network classifier that can run at wire speed reaching 100 Gbps on a network processor. In particular, we study approximations which allow us to efficiently compute the neural network output, while complying with the network processor limitations, which does not provide multiplication or other complex mathematical operations. The results show that the implementation is efficient and that the classification error is negligible.

ABSTRACT. This work introduces a Tunable Error Detection & Correction strategy (TED-C) aimed at improving the efficiency of adaptive voltage over-scaling (AVOS) in error-resilient applications. Through TED-C, the error coverage can be adjusted at run-time in order to accelerate the voltage scaling and achieve ultra-low energy consumption at the cost of quality-of-result (QoR). The mechanism is built upon elastic timing monitors, i.e., standard Razor-based timing monitors augmented with a tunable detection window and hardened with the aid of a dynamic short-path padding technique. Results collected over a FIR filter simulated with different realistic audio streams show TED-C achieves ultra-low energy-per-operation (up to 49.7% savings w.r.t. a standard Razor-driven AVOS) with negligible area overhead (0.3% vs. 25.8%) and low QoR degradation (0.72%).

ABSTRACT. The implementation of tactile data decoding on low power embedded system is crucial for the development of e-skin systems that are body worn and supplied by batteries. These embedded electronic systems have to comply with severe constraints imposed by the application, especially real-time functionality battery lifetime. One of the main challenges it to find a sweet spot between power consumption and performance as tactile data decoding implementation requires high amount of computational power. In this paper, we present the assessment of the system energy efficiency of tactile data decoding using an ultra-low power parallel platform. The work performs tactile data decoding using a support vector machine (SVM) based tensor kernel algorithm for input touch modalities classification. To improve the energy efficiency the system use a parallel ultra-low power (PULP) processor that satisfies the computational demands of the e-skin system by decoding the data streams generated by an array of tactile sensors. PULP allows to meet the computational requirements of the target application, without exceeding the power envelope of a 150 mW needed to have a long-term wearable device. We present the whole platform supported by experimental results that show the benefits in terms of low power and computational performance. The proposed algorithm runs more than 9x faster than an ARM Cortex M4 at 168MHz with the same consumption.

ABSTRACT. The growth of the IoT infrastructure requires the development of new devices able to harvest energy from the environment to power Wireless Sensor Network (WSN) nodes. Among the available sources (light, mechanical vibrations, temperature differences …), air flow can represent a good choice in many cases: we consider not only a natural wind, but also air flow in building pipelines or air flow around a moving vehicle (trains, trucks, cars …). Usually, an energy harvester EH device for IoT applications has centimeter-size dimensions: this constraint hinders the use of blade rotors, since the efficiency goes down at this scale. In this contribution, we present an EH device, called FLEHAP (Fluttering Energy Harvester for Autonomous Powering), which is based on an aeroelastic effect named fluttering. Via an electromagnetic coupling, the FLEHAP device can produce several mW in an air flow of 5 m/s. However, to efficiently transform the mechanical energy in electrical energy, a specialized electronics is needed. In particular, since the brake effect associated with the electromagnetic coupling strongly interacts with the fluttering dynamics, for the sake of the overall system efficiency, it is necessary to control the power drain from the coils. In our paper, we will describe our approach, based on an AC-DC switching converter, supervised by a low-power microcontroller circuit. The latter will be also able to collect data from sensors and send them through a dedicated wireless link.

ABSTRACT. Contemporary sensor-based robotic systems tend to use an ad-hoc combination of off-the-shelf components for onboard computational needs. The number and type of sensors present, the number and organization of the onboard processors, and the algorithms utilized for processing high bandwidth realtime sensor data present researchers and designers with a wide range of choices for which they are currently ill-equipped to evaluate the best options. We present a co-simulation framework for sensor-based mobile robots that allows for the power and performance analysis of custom embedded computing platforms for mobile robots with a range of onboard sensors. We demonstrate the utility of our co-simulation framework by analyzing the power and performance tradeoffs for the computational subsystem of a quadrotor unmanned aerial vehicle (UAV) with onboard camera sensor performing image processing tasks while operating in a custom virtual testbed.

ABSTRACT. Recently, most of researchers focus on low-power design for monitoring, and controlling different smart platforms. Generating reference voltages for power conditioning of these systems is one of the main design challenges of these systems. Therefore, bandgap reference (BGR) is required for providing a temperature, and supply independent reference voltage. This paper presents a CMOS lowvoltage

self-startup BGR circuit with improved power supply rejection ratio (PSRR). The proposed self-startup BGR circuit is based on the relation of a proportional to absolute temperature (PTAT), and complementary to absolute temperature (CTAT) references. A low-power BGR is implemented in 0.13 µm CMOS technology. The implemented BGR generates a reference voltage of 0.8 V, and consumes 9.5 µA form 3.3 V battery. Moreover, it achieves a high PSRR of 76 dB at 1KHz, while the temperature coefficient is 20 ppm/℃.

ABSTRACT. The microbial fuel cells (MFCs) are emerging energy harvesters that are promising for the autonomous supply of seafloors remote sensors. Regarding the low voltage and power, delivred by MFC a specifically designed electrical interface is required. The flyback in discontinuous conduction mode appears to be the best candidate to extract the maximum power delivered by the MFC, to isolate the user from the source and to boost the voltage to the one required by the energy buffering. A previous work highlighted the significant impact of the magnetic core loss of coupled inductances on the power efficiency decrease, mainly due to the hysteresis and magnetic saturation even at µ-scale energy harvesting. In this paper, we propose to remove the magnetic core to suppress this previously mentioned losses. The low harvested power (100 µW for 10th cm² electrodes) and low-size constraint i.e. m2-scale in seafloors remote sensors application allow to use 10th of cm2 air-core inductance. By plugging a 20-cm2 MFC delivering a maximum power of 90 µW at 0.3 V, the proposed converter achieved 60% efficiency experimentally. This figure correctly matches simulations in which a model of the coreless coupled inductances, extracted from experimental characterizations, is used. This work is the first to validate the concept of a flyback with coreless coupled inductances harvesting 10th of µWs.

ABSTRACT. Development of tactile sensing systems is motivated by the possibility of application in many domains such as robotics, prosthetics, and industrial automation. This paper provides a functionality assessment of an interface electronic circuit prototype for tactile sensing systems. The circuits are based on the DDC112U and an FPGA Xilinx Spartan-6. An experimental setup is carried out to measure the signals generated from a single tactile sensor. Experimental results validate the correct functionality of the proposed interface when the measured voltage and charge are analyzed in terms of the input force. Moving to the new system may pave the way towards the fully integrated SoC for the e-skin development.

ABSTRACT. In most robotic and biomedical applications, the interest for real-time embedded systems with tactile ability has been growing. For example in prosthetics, a dedicated portable system is needed for developing wearable devices. The main challenges for such systems are low latency, low power consumption and reduced hardware complexity. In order to improve hardware efficiency and reduce power consumption, approximate computing techniques have been assessed. This strategy is suitable for error-tolerant applications involving a large amount of data to be processed, which perfectly fits tactile data processing. This paper presents the first case study of applying Inexact Speculative Adders (ISA) to the FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) module within the Machine Learning algorithm of a tactile data processing system. The design has been synthesized and implemented on a Xilinx ZYNQ-7000 ZC702 device. Preliminary results have shown dynamic power reduction up to 40% and delay latency reduction up to 21% compared to a conventional CORDIC module, at the cost of a negligible average relative error of 0.049% for sine and 0.003% for cosine computations.

ABSTRACT. Internet-of-Things end-nodes with relatively limited production volume can take benefit from FPGA implementations of computing platforms based on dedicated computational units controlled by a soft processor core. The inherently multi-tasking nature of the processor operation demands for a cost-effective and energy-efficient multi-threaded execution, synthesized as multi-core architecture or multi-threaded single-core. This work presents an experimental exploration of microarchitecture design solutions for multi-threaded single-cores, specifically addressing soft processor core implementations on FPGA. We report detailed quantitative results on resource utilization, performance and energy efficiency of the different solutions, varying the pipeline organizations, thread pool size, active thread count and voltage.

ABSTRACT. The Convolutional Neural Network (CNN) algorithm allows fast and precise image recognition. Today, this ability is highly requested for quickly analysing complex video-streams in the embedded system domain. In this paper, we present an FPGA implementation designed addressing portability and power constraints. The designed architecture implements a full CNN model on an embedded FPGA device, reducing external memory requirement by 84% with respect to the software version. Power and performance characterization results show that the proposed implementation is 3 times more power efficient than a serial version on a general purpose CPU, and equivalently efficient to a 16-times parallelized version on the same processor.

ABSTRACT. This work presents a rad-hard by design (RHBD) 10-bit 1MHz SAR ADC for space applications. The goal is to design a radiation tolerant SAR ADC by using radiation-hardened by design (RHBD) techniques both at circuit and layout levels. The design takes into account the various effects of the radiation that could damage the circuits in ionising radiation environments. A conventional SAR ADC with charge redistribution capacitive DAC has been the starting point to whom RHBD techniques have been applied. The SAR was implemented and fabricated in a 0.15-um CMOS standard process by LFoundry. The prototype active area is 212x285 um2 and consumes 1.23mW. Measurement results show an ENOB equal to 9.6 bits in the band of interest, [1 - 10]KHz, at full-scale input voltage. The resulting figure of merit is 792 fj/conversion-step.

ABSTRACT. A low-power frequency-synthesizer PLL designed using the nanowire SGFET technology is proposed. The output frequency of the system is 10.3125 GHz, synthesized from a reference input of 156.25 MHz. The design utilizes a phase-frequency detector, a charge-pump, a 2nd order passive loop-filter, a current-starved ring voltage-controlled oscillator, and a frequency divider that consists of both TSPC and static flip-flops. The PLL has a wide tuning range from 2.8 GHz to 14.4 GHz, a phase margin of 54.53 degrees, a closed-loop bandwidth of 9.47 MHz, and a dc power consumption of 34.82 uW with 1V power supply.

ABSTRACT. This paper proposes a redundant sense amplifier for radiation-hardened SRAMs, based on a latched cross-coupled topology. First, the most common issues related to SRAMs reliability and performances in radiation environments are discussed. Then, after an analytical study on the transient effects induced by radiations, based on a systematic design flow, a novel redundant sensing scheme is presented and discussed. Simulation results, carried out in a standard 130-nm CMOS, demonstrate the effectiveness of the solution.

ABSTRACT. The size of counterfeiting activities is increasing day by day. These activities are encountered especially in electronics market. In this paper, a countermeasure against counterfeiting on intellectual properties (IP) on Field-Programmable Gate Arrays(FPGA) is proposed. FPGA vendors provide bitstream ciphering as an IP security solution such as battery-backed or non-volatile FPGAs. However, these solutions are secure as long as they can keep decryption key away from third parties. Key storage and key transfer over unsecure channels exposes risks for these solutions. In this work, physical unclonable functions (PUFs) has been used for key generation. Generating a key from a circuit in the device solves key transfer problem. Proposed system goes through different phases when it operates. Therefore, partial reconfiguration feature of FPGAs is essential for feasibility of proposed system.

ABSTRACT. This paper presents an analytical model of a tapped shift-register based delay generator, which is currently implemented in the High Momentum Particle Identification Detector (HMPID) at CERN and will be upgraded in the coming years. This work aims to verify whether this delay generator can be optimized to provide a delay range of 525 ns with a resolution of 1 ns. In particular, this paper studies how the clock jitter affects the delay generated and its linearity and predict how the current architecture will perform at a higher frequency of operation. The conclusions drawn via the analytical model, are then verified using both a simulation model and an FPGA implementation of the delay generator.

ABSTRACT. This paper presents the feasibility study of a low-power 5-bit synchronous current-mode SAR ADC primarily targeted for ultra high speed applications. The circuit uses a voltage-current converter at the front end and a current steering DAC. The discrete analog output is digitized by a latch and a standard SAR logic in its feedback by using a binary search algorithm. The proposed scheme exploits the compatibility of SAR ADCs with advanced technology nodes and provides an excellent opportunity to achieve ultra high speeds. The circuit exhibits a sampling rate upto 4 GS/sec with a full scale differential current of 1 mA(pk-pk) or differential voltage of 300 mV(pk-pk). The proposed circuit is designed in a 28-nm CMOS process, achieves a figure of merit of 18.3 fJ/conv.-step and dissipates about 2.35 mW with a 0.9 V supply voltage.

ABSTRACT. Asynchronous circuit design has been introduced many decades ago, however until now with the limited industry application. This paper summarizes the basic asynchronous principles and techniques, as well as the latest developments as well as the outlook.

ABSTRACT. This paper presents an overview of a family of asynchronous arbitration primitives designed to increase the resilience and efficiency of the new generation of circuits and systems. We cover primitives for synchronisation and decision-making with an emphasis on interfacing analog and digital worlds, sampling of non-persistent signals, and efficient handling of correlated sensor events.

ABSTRACT. Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for correct system-level operation. Asynchronous interconnection networks naturally provide such asynchrony, however their commercial uptake depends on the capability to overcome two fundamental barriers: their area and dynamic power overhead as well as the limited computer-aided design (CAD) tool support for their automated design. This paper presents a novel design point for on-chip asynchronous communication, combining design flexibility with small footprint and cost effectiveness. It relies on a parameterizable switching fabric designed on top of a two-phase communication protocol and a bundled-data encoding scheme, combined with a predictable hierarchical synthesis flow with mainstream industrial tools.

ABSTRACT. For High Performance Computing (HPC), the never ending quest of additional computing capability is hitting strong limits, mostly the power wall and the memory wall. The 3D technology by using so-called TSVs (Through Silicon Via) offers the possibility to integrate more cores, closer to the memories, with reduced power consumption thanks to smaller communication distances. For such 3D technologies, the main challenges are to design energy efficient 3D communication infrastructure, to offer test strategy and to handle related power and thermal dissipation issues.

The Globally Asynchronous Locally Asynchronous (GALS) paradigm has been widely studied in order to decouple the timing domains in large System-on-Chip. GALS is a perfect enabler of Network-on-Chip communication infrastructure, where IPs are locally synchronous while the Network-on-Chip is fully asynchronous. In this context, we present an innovative 3D asynchronous Network-on-Chip as a solution to implement efficiently a 3D GALS system, providing robust inter layer communication, avoiding inter layer clocking, and providing fast and energy efficient 3D links. Recent circuit results exhibits the feasibility of such approach and paves the way to further system perspectives.

ABSTRACT. Real-time systems need a time-predictable computing platform. Computation, communication, and access to shared resources needs to be time-predictable. We use time division multiplexing to statically schedule all computation and communication resources, such as access to main memory or message passing over a network-on-chip. We use time-driven communication over an asynchronous network-on-chip to enable time division multiplexing even in a globally asynchronous, locally synchronous multicore architecture. Using time division multiplexing at all levels of the architecture yields in a time-predictable multicore processor where we can statically analyze the worst-case execution time of tasks.

ABSTRACT. This paper presents a perceptron circuit which can be implemented into sensor analog front-end consistent with neural network-based machine learning. We introduce a DAC-based multiplier in the perceptron circuit, where the DAC is used as a programmable resistor. Compared with a traditional transconductor-based multiplier, the precision of our multiplier is formulated only by the digital codes, and it has a wide input range and a good temperature dependency. The simulation result demonstrates the DAC-based multiplier amplifies smoothly analog signal by the digital codes.

ABSTRACT. A clock recovery gated phase locked loop (GPLL) for periodically missing input signals and 100% amplitude shift keying modulation is presented. The On-Off keying scheme leads to long periods without an RF signal to extract. This poses special requirements that can be met by using gated PFDs. The power control technique used in this implant periodically shorts the receiving coil, thus limiting the received energy. However, not only does this entail another absence of the RF signal, but it can also lead to a stationary cycle slip, where the VCO performs one cycle too much or less compared to the RF signal. The number of cycle slips can be significantly reduced by implementing two additional PFDs with inverse reset conditions. The proposed PLL with gated PFDs was fabricated and measured in a 350nm high voltage CMOS process. Simulations and performance yield consistent results.

ABSTRACT. Personalized drug dosage is crucial to ensure optimal benefit in patient’s treatments. Therefore, many efforts are done in developing integrated, low-cost and portable point- of-care sensing systems able to continuously monitor the drug concentration. To satisfy this request, a portable multi-channel system is here presented and validated. The system is able to run different electrochemical techniques independently on each channel. Thanks to the flexibility of the system it is possible to configure it for different medical applications, as for anesthesia practices. The Raspberry Pi has been chosen as main control unit since it offers high performances and excellent features with low- costs.

ABSTRACT. This paper describes a readout integrated circuit (ROIC) for a photoresistive image sensor incorporating wheatstone bridge configuration with a variable-gain switched-capacitor amplifier. A 12-bit R-2R ladder digital-to-analog converter (DAC) is used for on-chip calibration. The bias voltage of the bridge is supplied by an on-chip DAC and made programmable between 0 to 1.8 Volts for ROIC performance optimization. This image sensor and ROIC system is intended to be used as an endoscope camera which demands strict silicon area and low power consumption requirements. A sample 1x16 line sensor is used for proof of concept. The ROIC is designed for the target 30 frames per second output data rate for a 400x1 line sensor. This work focuses on the analog signal processing chain of the ROIC. The column-wise design makes the ROIC scalable for larger image sensor sizes. The nominal (base) resistance of each detector is assumed to have a variation of (+-10%). The proposed ROIC is designed in 0.18 um CMOS process and the system is verified with post-layout simulations.