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| 08:30 | Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing SPEAKER: Wim Dobbelaere ABSTRACT. The application of DPAT at the final testing stage is evaluated. Analog fault coverage simulations and experimental data prove that the method effectively screens out defective devices that are not caught by traditional specification-based tests. |
| 09:00 | Effective DC Fault Models and Testing Approach for Open Defects in Analog Circuits SPEAKER: Baris Esen ABSTRACT. This paper presents a new open-gate DC fault model. Experimental results on fabricated circuits are used to validate the proposed model. Also, a new testing approach for the open defects in analog circuits is discussed. |
| 09:30 | Fault Simulation for Analog Test Coverage SPEAKER: Suriyaprakash Natarajan ABSTRACT. A practical fault simulation methodology that leverages mixed-signal simulation to measure the coverage of manufacturing tests on gross faults in analog circuits is presented. Results on a high speed serial interface demonstrate its value. |
| 08:30 | Defect Tolerance for CNFET-based SRAMs SPEAKER: Tianjian Li ABSTRACT. This paper proposes a novel redundancy architecture for CNFET-based SRAMs to efficiently repair the asymmetrically distributed faults induced by CNTs. An analytical model is built to guide the exploration of the redundancy architecture. |
| 09:00 | A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits SPEAKER: Yong-Xiao Chen ABSTRACT. A BISR scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms is proposed. Simulation results show that the BISR scheme can provide higher repair rate than existing BISR schemes by consuming fewer redudancies. |
| 09:30 | EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays SPEAKER: Insik Yoon ABSTRACT. This paper presents resistive & capacitive defects and the corresponding faults. A novel MBIST architecture and associated circuits are presented for measuring thermal stability in STT-MRAM bits for characterization and manufacturing tests. |
| 08:30 | Statistical Outlier Screening as a Test Solution Health Monitor SPEAKER: David Shaw ABSTRACT. Variance in die parametric outlier counts that presents either test hardware commonality or wafer map patterns are an indicator of overall test solution health. Investigating these occurrences leads to improved test stability and solution durability. |
| 09:00 | Accurate Anomaly Detection Using Correlation-Based Time-Series Analysis in a Core Router System SPEAKER: Shi Jin ABSTRACT. A feature-categorization-based anomaly detector is designed to monitor a complex core router system. Furthermore, a correlation analyzer is implemented to remove irrelevant and redundant features. Synthetic anomalies are used to validate the proposed anomaly detector. |
| 09:30 | Harnessing Process Variations for Optimizing Wafer-level Probe-Test Flow SPEAKER: Ali Ahmadi ABSTRACT. We propose a methodology for dynamically selecting an optimal probe-test flow which reduces test cost without jeopardizing test quality. It is based on e-test signature which reflects how process variations have affected this particular wafer. |
IEEE 1687.1 is under discussion, but what is the need, what is the problem, and how could it be solved.
| 08:30 | IEEE P1687.1: Opening New Portals to IJTAG Networks SPEAKER: Jeff Rearick ABSTRACT. One valuable feature of IEEE 1687 that was left under-specified in the standard is the use of non-TAP interfaces (e.g. I2C, SPI, etc.) to access the serial network. This presentation outlines the approach being taken by the emerging P1687.1 Working Group to enable alternative interfaces. |
| 09:00 | Extending the application of IEEE 1687 SPEAKER: Tom Waayers ABSTRACT. TBA |
| 09:30 | P1687.1 – Beyond the TAP SPEAKER: Nitin Parimi ABSTRACT. TBA |
Organizer: Bob Bartlett, Advantest
We will examine current ATE mmWave production test requirements and solutions. This session will highlight architectures, some key measurement challenges with focus on the contact and launch techniques required for testing wafer and packaged devices to 81GHz.
| 08:30 | Package Interconnect Options for mmWave Applications SPEAKER: Tony Smith ABSTRACT. We will discuss the options and considerations regarding the socket and interconnect technology used to connect the package with the board interface to the ATE system for mmWave applications. |
| 09:00 | Challenges with high volume mmWave test cells SPEAKER: John Shelley ABSTRACT. This will present the challenges encountered in developing a test cell for mmWave in high volume production test. Before and after results are discussed after two years of development and customer trials, including ATE, handler, and interface challenges, as well as future test concepts. |
| 09:30 | Millimeter Systems for Production SPEAKER: Roger McAleenan ABSTRACT. This talk discusses Advantest's "application extensions" that add features required for the application and enable native V93000 to be replicated. All usual V93000 resources are brought to DUT with a standard docking interface. Additional application requirements are added, covering the main specifications and their unique features.
Abstract: We have implemented the concept of application extensions for mmWave that add features required for the application and extend the 93000 base platform. The test head resources are brought to the DUT through the tester docking interface allowing us to use standard DUT board interfaces for final test and direct probe. We’ll discuss Millimeter extension requirements and the key features implemented. |
| 10:30 | A Suite of IEEE 1687 Benchmark Networks SPEAKER: Anton Tsertov ABSTRACT. We present a set of long-waited-for benchmarks representing challenging IEEE1687 network examples for automatic processing by algorithms and parsers facilitating both tool evaluation and comparison of experimental results across research groups. |
| 11:00 | Accessing 1687 Systems Using Arbitrary Protocols SPEAKER: Michele Portolan ABSTRACT. upon release, the IEEE 1687 standard left open the possibility of using alternate access methods than the JTAG Test Access Port, but gave no provision on how this could be done. In this paper, we propose a solution that is able to support access to the full 1687 functionalities through any generic interface. |
| 11:30 | Upper-Bound Computation for Optimal Retargeting in IEEE 1687 Networks SPEAKER: Farrokh Ghani Zadegan ABSTRACT. In retargeting for 1687’s reconfigurable scan-paths, finding scan vectors that are optimal w.r.t. application time is a hard problem. Our method supports the vector search by reducing the search space without removing the optimal vector. |
| 10:30 | Low Cost Ultra-Pure Sine Wave Generation with Self Calibration SPEAKER: Yuming Zhuang ABSTRACT. This paper presents a novel low cost method for generating ultra-pure sine wave, using readily available devices and innovative algorithm to iteratively remove distortions from the signal, whose high purity is verified by measurement results. |
| 11:00 | RF Test Accuracy and Capacity Enhancement on ATE for Silicon TV Tuners SPEAKER: Anant Verma ABSTRACT. This paper presents a scheme that enhances the NF test accuracy to ±0.5dB on ATE, enabling us to specify maximum NF numbers in datasheets and test them in production. This scheme also expands the ATE test capacity to include RF level testing. |
| 11:30 | SERDES External Loopback Test Using Production Parametric-Test Hardware SPEAKER: Shalini Arora ABSTRACT. This paper describes a production load-board designed to achieve tester access on the SERDES pins using resistor network. External loopback could be operated successfully up to 20Gbps on this load-board without sacrificing parametric test capability. |
| 10:30 | What We Know After Twelve Years Developing and Deploying Test Data Analytics SPEAKER: Kenneth Butler ABSTRACT. TI and Portland State University have developed test data analytical methods for quality screening, burn-in minimization, high cost test replacement, and operations monitoring. In this paper, key findings amassed during this time are summarized. |
| 11:00 | Supply-Voltage Optimization to Account for Process Variations in High-Volume Manufacturing Testing SPEAKER: Krishnendu Chakrabarty ABSTRACT. We propose a method to identify supply-voltage levels to test semiconductor chips based on the process variations experienced by them, while also adapting these supply-voltage levels based on the chip locations on the wafer. |
| 11:30 | Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages SPEAKER: Chun-Kai Hsu ABSTRACT. We propose a framework for discovering comprehensible correlations between process variations and systematic failures. The framework analyzes process parameters and production test measurements using a biclustering technique, and has been verified by an industrial dataset. |
| 10:30 | Built-In Self-Test for Micro-Electrode-Dot-Array Digital Microfluidic Biochips SPEAKER: Zipeng Li ABSTRACT. A digital microfluidic biochip (DMFB) based on MEDA architecture is an attractive platform. MEDA biochips must be adequately tested. We present an efficient built-in self-test (BIST) architecture for MEDA biochips to identify faulty cells. |
| 11:00 | Online Slack-Time Binning for IO-Registered Die-to-Die Interconnects SPEAKER: Shi-Yu Huang ABSTRACT. A low-cost Slack-Time Monitor is proposed for IO-registered interconnects in a 2.5D IC. Two techniques are introduced: (1) tunable guard-band technique, and (2) offset compensation technique. With these techniques, online slack-time binning can be performed. |
| 11:30 | Anticipated Test Challenges of Emerging Devices SPEAKER: Rob Aitken |
Organizer: Dave Amstrong, Advantest
| 10:30 | Moore’s Law is Done and Heterogeneous Integration is Taking Off SPEAKER: Dave Armstrong |
| 11:00 | Probe Challenges are Changing Rapidly SPEAKER: Marc Loranger |
| 11:30 | Test and Supply Chain Challenges for Heterogeneous Integration SPEAKER: Bill Eklow |
| 14:00 | Logic Characterization Vehicle Design Reflection via Layout Rewiring SPEAKER: Phillip Fynan ABSTRACT. Yield learning requires test vehicles that reflect customer designs. A cell-aware test vehicle is constructed by removing routing from the layout, then rewiring the cells into a new structure that is ultra testable and diagnosable. |
| 14:30 | Test Chip Design for Optimal Cell-Aware Diagnosability SPEAKER: Soumya Mittal ABSTRACT. Yield learning in a new technology requires numerous types of test chips. This work describes a "Design for Diagnosis" methodology to achieve optimal cell-aware diagnosis within a logic characterization vehicle. |
| 15:00 | Advanced Node Product and Technology Enablement Vehicles SPEAKER: Mike Bourland ABSTRACT. Advanced node product and technology enablement requires a different kind of vehicle. Advanced node product enablement vehicle architectures need to drive design flow flush, IP development, yield ramp, advanced diagnostics and fault models and parametric sensitivity analysis and correlation. Time to data drives time to actionable information and actions drive time to market, time to yield and time to margin. This talk takes a look at a fabless SoC view of managing technology complexity by way of product and technology enablement vehicles. |
| 14:00 | Mixed-Signal ATE Technology and its Impact on Today’s Electronic System Platforms SPEAKER: Gordon Roberts ABSTRACT. The case is made in this talk that analog/mixed-signal semiconductor test technology of the seventies and eighties has been at the forefront of many of today’s analog SOC design approaches. |
| 14:30 | Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices SPEAKER: Dave Armstrong ABSTRACT. Explores achieving KGD by testing bare die just prior to assembly. After showing ROI for this test step it discusses real-life experience handling and contacting thinned high-bump-count , high-power devices while testing at temperature extremes. |
| 15:00 | Test time efficient group delay filter characterization technique using a discrete chirped excitation signal SPEAKER: Peter Sarson ABSTRACT. To measure a filter’s group delay in production is never an easy task and to measure the group delay characteristic in quick and timely manner is difficult to say the least. This paper will discuss a simple method that expands on the author’s previous works that will demonstrate how to measure the group delay of a filter and how accurately the technique correlates to measurements of the silicon performance made in the lab. The test time saving and stability of results will be shown as well as the advantages of the technique with regard to having full characterization data available in a production program. Finally it will be shown how the work can be further developed to a potentially more efficient technique. |
| 14:00 | Securing Digital Microfluidic Biochips by Randomizing Checkpoints SPEAKER: Jack Tang ABSTRACT. We present an analysis of a cyberphysical digital microfluidic biochip (DMFB) system prone to malicious modification of routes, and propose a defense based on spatio-temporal randomized checkpoints using CCD cameras. |
| 14:30 | Machine Learning-based Defense Against Process-Aware Attacks on Industrial Control Systems SPEAKER: Anastasis Keliris ABSTRACT. Industrial Control Systems are under attack! We will demonstrate categories of cyberattacks, intelligent process-aware attacks and our machine learning-based defense mechanism, using a Hardware-in-the-loop testbed of a benchmark chemical process. |
| 15:00 | Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization SPEAKER: Md Mahbub Alam ABSTRACT. This paper exploits all possible paths in look-up tables (LUTs) in FPGAs and uses path delay characteristics to detect recycled FPGAs. Supervised and unsupervised based learning methods are proposed for classification. |
| 14:00 | Four Challenging Insights about Fault Coverage SPEAKER: Jeff Rearick ABSTRACT. This presentation challenges the orthodoxy surrounding one of our fundamental metrics: fault coverage. Four insights are shared which should make our industry at least reflective, perhaps nervous, and certainly motivated to innovate. |
| 14:30 | Advanced Test Methodology for Complex SoCs SPEAKER: Mahmut Yilmaz ABSTRACT. This paper presents the latest flexible test architecture for NVIDIA’s multi-billion transistor mobile SOC and GPU chips. This architecture enables ultra-low pin count testing, test data reuse, efficient test scheduling, and lower test cost. |
| 15:00 | The DFT Challenges and Solutions for the ARM Mali-Mimir GPU SPEAKER: Teresa Mclaurin ABSTRACT. The DFT and test challenges faced, and the solutions applied, to the ARM Mali-Mimir GPU are described in this presetation. DFT techniques have been utilized to address the challenges of testing a large design using a hierarchical test insertion methodology. Special logic has been added to ensure testability with regard to multiple asynchronous clock domains that are controlled by a single clock pin. As always, with IP, the main challenge is to create a flow that is portable to many different partners and that utilizes popular EDA tools. This paper also discusses the use of the internal ARM MBIST standardized interface in conjunction with the hierarchical test flow. |
This special session discusses challenges and solutions in dealing with manufacturing, test and reliability of emerging non volatile memories, and in particular spin transfer torque magnetic memories (STT-MRAM). The speakers from key industries in this emerging technology present their perspectives on test and reliability solutions to enable high volume production and utilization of this emerging technology.
| 14:00 | STTRAM Overview -- Circuit and Architecture Perspective SPEAKER: Helia Naeimi ABSTRACT. TBA |
| 14:30 | TBABIST Design for Characterization and Testing of Embedded STT-MRAM SPEAKER: Saman Adham ABSTRACT. TBA |
| 15:00 | Tailoring Design and Test Methodologies to Validate STT-MRAM as High-Performance Nonvolatile RAM SPEAKER: Seung H. Kang ABSTRACT. TBA |
*15-minute tributes are devoted to honor Professor Edward J. McCluskey at the end of this keynote session.
TITLE: Hardware Inference Accelerators for Machine Learning
NAME: Rob A. Rutenbar, Professor, UIUC
ABSTARCT:
Machine learning (ML) technologies have revolutionized the ways in which we interact with large-scale, imperfect, real-world data. As a result, there is rising interest in opportunities to implement ML efficiently in custom hardware. We have designed hardware for one broad class of ML techniques: Inference on Probabilistic Graphical Models (PGMs). In these graphs, labels on nodes encode what we know and “how much” we believe it; edges encode belief relationships among labels; statistical inference answers questions such as “if we observe some of the labels in the graph, what are most likely labels on the remainder?” These problems are interesting because they can be very large (e.g., every pixel in an image is one graph node) and because we need answers very fast (e.g., at video frame rates). Inference done as iterative Belief Propagation (BP) can be efficiently implemented in hardware, and we demonstrate several examples from current FPGA prototypes. We have the first configurable, scalable parallel architecture capable of running a range of standard vision benchmarks, with speedups up to 40X over conventional software. We also show that BP hardware can be made remarkably tolerant to the low-level statistical upsets expected in end-of-Moore’s-Law nanoscale silicon and post-silicon circuit fabrics, and summarize some effective resilience mechanisms in our prototypes.
BIO: Rob A. Rutenbar received the Ph.D. degree from the University of Michigan, Ann Arbor, in 1984. From 1984 to 2009, he was faculty at Carnegie Mellon, where he held the Stephen J. Jatras (E’47) Chair in Electrical and Computer Engineering. In 2010 he joined the University of Illinois at Urbana-Champaign, where he is currently the Abel Bliss Professor and Head of Computer Science. His research has focused in three broad areas: tools for a variety of IC design problems; methods to manage the messy statistics of nanoscale chip designs; and custom silicon architectures for challenging tasks such as speech recognition and machine learning. His work has been featured in venues ranging from EETimes to the Economist magazine. He is a Fellow of the ACM and IEEE.